74LVC823A データシートの表示（PDF） - NXP Semiconductors.
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74LVC823A
NXP Semiconductors.
74LVC823A Datasheet PDF : 21 Pages
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Nexperia
74LVC823A
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
6. Functional description
Table 3. Function table [1]
Operating mode
Input
OE
MR
CE
CP
Dn
Clear
L
L
X
X
X
Load and read register L
H
L
l
L
H
L
h
Load register and
H
H
L
l
disable outputs
H
H
L
h
Hold
L
H
H
NC
X
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition
Z = high-impedance OFF-state
= LOW to HIGH level transition
X = don’t care
NC = no change
7. Limiting values
Internal
flip-flop
L
L
H
L
H
NC
Output
Qn
L
L
H
Z
Z
NC
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max
Unit
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
VO
output voltage
VI < 0 V
VO > VCC or VO < 0 V
HIGH or LOW state
3-state
0.5 +6.5
V
50 -
mA
[1] 0.5 +6.5
V
-
50
mA
[2] 0.5
VCC + 0.5
V
[2] 0.5 +6.5
V
IO
ICC
IGND
Tstg
Ptot
output current
supply current
ground current
storage temperature
total power dissipation
VO = 0 V to VCC
Tamb = 40 C to +125 C
-
50
mA
-
100
mA
100 -
mA
65 +150
C
[3] -
500
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO24 packages: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP24 and TSSOP24 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN24 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
74LVC823A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2013
© Nexperia B.V. 2017. All rights reserved
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