AD9136BCPZ データシートの表示（PDF） - Analog Devices
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AD9136BCPZ Datasheet PDF : 117 Pages
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Data Sheet
AD9135/AD9136
LATENCY VARIATION SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.
Table 7.
Parameter
DAC LATENCY VARIATION
SYNC On
PLL Off
PLL On
Min
Typ
Max
Unit
0
−1
1
DAC clock cycles
+1
DAC clock cycles
JESD204B INTERFACE ELECTRICAL SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 8.
Parameter
JESD204B DATA INPUTS
Input Leakage Current
Logic High
Logic Low
Unit Interval
Common-Mode Voltage
Differential Voltage
VTT Source Impedance
Differential Impedance
Differential Return Loss
Common-Mode Return Loss
DIFFERENTIAL OUTPUTS (SYNCOUTx±)2
Output Differential Voltage
Normal Swing Mode
High Swing Mode
Output Offset Voltage
DETERMINISTIC LATENCY
Fixed
Variable
SYSREF± to LOCAL MULTIFRAME
COUNTER (LMFC) DELAY
Symbol Test Conditions/Comments
UI
VRCM
R_VDIFF
ZTT
ZRDIFF
RLRDIF
RLRCM
TA = 25°C
Input level = 1.2 V ± 0.25 V, VTT = 1.2 V
Input level = 0 V
AC-coupled, VTT = SVDD121
At dc
At dc
VOD
Register 0x2A5[0] = 0
Register 0x2A5[0] = 1
VOS
Min Typ Max Unit
10
−4
94
−0.05
110
80 100
8
6
µA
µA
714 ps
+1.85 V
1050 mV
30 Ω
120 Ω
dB
dB
192
341
1.19
4
235 mV
394 mV
1.27 V
17
PClock3 cycles
2
PClock3 cycles
DAC clock cycles
1 As measured on the input side of the ac coupling capacitor.
2 IEEE Standard 1596.3 LVDS compatible.
3 PClock is an AD9135/AD9136 internal processing clock and equals the lane rate ÷ 40.
Rev. C | Page 9 of 117
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