MX29F800CT データシートの表示（PDF） - Integrated Device Technology

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MX29F800CT

8M-BIT [1024K x 8 / 512K x 16] SINGLE VOLTAGE 5V ONLY FLASH MEMORY

Integrated Device Technology 

MX29F800C T/B

REQUIREMENTS FOR READING ARRAY DATA

Read array action is to read the data stored in the array out. While the memory device is in powered up or has

been reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored

in array, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address

of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being

read out will be displayed on output pin for microprocessor to access. If CE# or OE# is Vih, the output will be in

tri-state, and there will be no data displayed on output pin at all.

After the memory device completes embedded operation (automatic Erase or Program), it will automatically re-

turn to the status of read array, and the device can read the data in any address in the array. In the process of

erasing, if the device receives the Erase suspend command, erase operation will be stopped after a period of

time no more than Treadyand the device will return to the status of read array. At this time, the device can read

the data stored in any address except the sector being erased in the array. In the status of erase suspend, if user

wants to read the data in the sectors being erased, the device will output status data onto the output. Similarly, if

program command is issued after erase suspend, after program operation is completed, system can still read ar-

ray data in any address except the sectors to be erased.

The device needs to issue reset command to enable read array operation again in order to arbitrarily read the

data in the array in the following two situations:

1. In program or erase operation, the programming or erasing failure causes Q5 to go high.

2. The device is in auto select mode.

In the two situations above, if reset command is not issued, the device is not in read array mode and system

must issue reset command before reading array data.

WRITE COMMANDS/COMMAND SEQUENCES

To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle,

all address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising

edge of CE# and WE#.

Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets

of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid

command will bring the device to an undefined state.

RESET# OPERATION

Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in

program or erase operation, the reset operation will take at most a period of Tready for the device to return to

read array mode. Before the device returns to read array mode, the RY/BY# pin remains low (busy status).

When RESET# pin is held at GND±0.3V, the device consumes standby current(Isb).However, device draws larg-

er current if RESET# pin is held at Vil but not within GND±0.3V.

It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memo-

ry will be reset during system reset and allows system to read boot code from flash memory.

P/N:PM1493

REV. 1.2, JUL. 05, 2012

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