NCP4355BDR2G データシートの表示（PDF） - ON Semiconductor
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NCP4355BDR2G Datasheet PDF : 17 Pages
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NCP4355
OFF mode is detected. In OFF mode SW1 is switched off
and no IONOFF current is going through ON/OFF pin. The
primary controller’s REM pin voltage increases and primary
IC goes in to off mode.
IBIASV current flow from VSNS pin to feedback divider
is also activated when OFF mode is detected. This current
increases voltage at VSNS pin and due to it voltage OTA
sinks reduced current through regulation optocoupler. OTA
stops to sink current when VSNS voltage drops below VREF.
IBIASV current disappears when VSNS voltage is lower than
90% of VREF. This feature helps to avoid primary side
switching when OFF mode is detected at secondary side and
primary side is waiting for correct information at REM pin.
Minimum Output Voltage Detection (except NCP4355A)
Minimum output voltage level defines primary controller
restart from OFF mode. It can be set by shared voltage
divider with voltage regulation loop. When VMIN voltage
drops below VREFM, OFF mode is ended and primary
controller restarts.
NCP4355A has no external adjustment and uses the
internal minimum voltage level specified by minimum
falling operation supply voltage and special load detection
circuit for faster detection of load connection (T2, R16 and
R17 at Figure 24). Principe of load connection detection is
that when load is connected, output capacitor C1 is
discharged faster than C6 capacitor by IC supply current.
Voltage across D3 increases and when there is enough
voltage to open T2 some current is injected into OFFDET
divider. Voltage at OFFDET pin goes above 10% of VCC and
OFF mode ends. This circuit can also be used with B and C
versions to dramatically speed up wakeup time from OFF
mode. If this circuit is not used, it is necessary to wait for C6
discharge below VCC UVLO falling level before the
primary controller is restarted.
LED Driver (except NCP4355C)
LED driver is active when VCC is higher than VCCMIN
and output voltage is in regulation (it is off during OFF
mode). LED driver consists of an internal power switch
controlled by PWM modulated logic signal and an external
current limiting resistor R3. LED current can be computed
by Equation 5
ILED
+
VOUT
* VF_LED
R3
(eq. 5)
PWM modulation is used to increase efficiency of LED.
Operation in OFF Mode Description
Operation waveforms in off mode and transition into OFF
mode with primary controller are shown in Figure 28.
Figure shows waveforms from the first start (1) of the
convertor. At first, primary controller charges VCC
capacitor over the VCCON level (2). When primary VCC is
over this level (3), primary controller starts to operate and
VOUT is slowly rising according to primary controller start
up ramp to nominal voltage (4). When VOUT is high enough,
VCC capacitor is charged from auxiliary winding.
Primary FB pin voltage is above regulation range until
VOUT is at set level. Once VOUT is at set level, the secondary
controller starts to sink current from optocoupler LED’s and
primary FB voltage is stabilized in regulation region. With
nominal output power (without skip mode) OFFDET pin
voltage is higher than VOFFDETTH (typically 10% of VCC).
After some time, the load current decreases to low level
(5) and primary convertor uses skip mode (6) to keep
regulation of output voltage at set level and save some
energy. The skip mode consists of few switching cycles
followed by missing ones to provide limited energy by light
load. The number of missing cycles allows regulation for
any output power.
While both C1 and C2 are discharged during the missing
cycles, C2 discharge will be faster than C1 without output
current, VOFFDET drops below VOFFDETTH and OFF mode
is detected (7). This situation is shown in Figure 27 in detail.
When OFF mode is detected, current into ONOFF pin stops
to flow (7) and voltage at primary REM pin increases over
threshold level that forces primary controller into OFF
mode. Internal pull−up current IBIASV is switched on (7),
VSNS pin voltage increases (thanks to IBIASV) and voltage
amplifier sinks reduced current at time (8), when VSNS is
higher than VREF (9), to keep primary FB voltage below
switching level until REM pin voltage is high enough.
IBIASV current stops when VSNS voltage drops below 90%
of VREF.
Discharging of C1 continues (10) until output voltage
drops below level set by voltage divider at VMIN pin
(except NCP4355A where minimum VOUT is defined only
by VCC UVLO) (11). ONOFF current starts to flow,
primary REM voltage decreases and primary VCC voltage
is rising (12). Primary controller starts to operate, when
VCC voltage is enough and FB voltage is at regulation area
(13). Output capacitor C1 is recharged (14) to set voltage. If
there is still light load condition primary controller goes to
skip mode (15) again and after some time secondary
controller detects OFF mode by very light or no load
condition (16) and whole cycle is repeated.
Fast Restart From OFF Mode
The IC ends OFF mode when a load is connected to the
output and VOUT is discharged to VMIN level. There exists
another connection that allows transition to normal mode
faster without waiting some time for VOUT to discharge to
VMIN (it is necessary to use it with NCP4355A). This
schematic is shown at Figure 24 in dashed box. The basic
idea is that C6 is discharged by the IC faster than C1 by
output load in OFF mode. When an output load is applied,
capacitor C1 is discharged faster and this creates the voltage
drop at D3. When there is enough voltage at D3, T2 is
conducting and current is injected into the OFFDET divider
through R16. OFFDET voltage higher than 10% of VCC
ends OFF mode and ON/OFF current starts to flow. Primary
controller leaves OFF mode because voltage at REM pin
increase above OFF mode detection threshold.
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