74HC4046APW データシートの表示（PDF） - NXP Semiconductors.

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74HC4046APW

Phase-locked loop with VCO

NXP Semiconductors. 

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

8. Functional description

The 74HC4046A; 74HCT4046A is a phase-locked-loop circuit that comprises a linear VCO and

three different phase comparators (PC1, PC2 and PC3). It has a common signal input amplifier and

a common comparator input (see Fig. 1). The signal input can be directly coupled to a large voltage

signal, or indirectly coupled (with a series capacitor) to a small voltage signal. A self-bias input

circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive

low-pass filter, the 74HC4046A; 74HCT4046A forms a second-order loop PLL. The excellent VCO

linearity is achieved by the use of linear op amp techniques.

8.1. VCO

The VCO requires one external capacitor C1 (between pins C1A and C1B) and one external

resistor R1 (between pins R1 and GND). Alternatively, it requires two external resistors R1 and

R2 (between pins R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine the

frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if necessary

(see Fig. 4).

The high input impedance of the VCO simplifies the design of the low-pass filters by giving

the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter,

a demodulator output of the VCO input voltage is provided at pin DEM_OUT. In contrast to

conventional techniques, where the DEM_OUT voltage is one threshold voltage lower than the

VCO input voltage, the DEM_OUT voltage equals the VCO input. If DEM_OUT is used, a series

resistor (Rs) should be connected from pin DEM_OUT to GND. If unused, DEM_OUT should be

left open. The VCO output (pin VCO_OUT) can be connected directly to the comparator input (pin

COMP_IN) or connected via a frequency divider. When the VCO input DC level is held constant,

the VCO output signal has a duty cycle of 50 % (maximum expected deviation 1 %). A LOW-level

at the inhibit input (pin INH) enables the VCO and demodulator, while a HIGH-level turns off both to

minimize standby power consumption.

The only difference between the 74HC4046A and 74HCT4046A is the input level specification of

the INH input. A HIGH on the INH input disables the VCO section. The input level specification for

the SIG_IN and COMP_IN inputs are identical for both 74HC4046A and 74HCT4046A.

8.2. Phase comparators

The input signal can be coupled to the self-biasing amplifier at pin SIG_IN, when the signal swing is

between the standard HC/T family input logic levels. Capacitive coupling is required for signals with

smaller swings.

8.2.1. Phase Comparator 1 (PC1)

This circuit is an EXCLUSIVE-OR network. The signal and comparator input frequencies (fi) must

have a 50 % duty cycle to obtain the maximum locking range. The transfer characteristic of PC1,

assuming ripple (fr = 2fi) is suppressed, is:

where:

• VDEM_OUT is the demodulator output at pin DEM_OUT

• VDEM_OUT = VPC1_OUT (via low-pass filter)

The phase comparator gain is:

74HC_HCT4046A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 6 August 2019

© Nexperia B.V. 2019. All rights reserved

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