74HC4046APW データシートの表示（PDF） - NXP Semiconductors.

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74HC4046APW

Phase-locked loop with VCO

NXP Semiconductors. 

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

8.2.2. Phase Comparator 2 (PC2)

PC2 is a positive edge-triggered phase and frequency detector. When the PLL uses this

comparator, positive signal transitions control the loop and the duty cycles of SIG_IN and

COMP_IN are not important. PC2 comprises two D-type flip-flops, control gating and a 3-state

output stage. The circuit functions as an up-down counter (see Fig. 4) where SIG_IN causes an

up-count and COMP_IN a down count. The transfer function of PC2, assuming ripple (fr = fi) is

suppressed, is:

where:

• VDEM_OUT is the demodulator output at pin DEM_OUT

• VDEM_OUT = VPC2_OUT (via low-pass filter)

The phase comparator gain is:

VDEM_OUT is the resultant of the initial phase differences of SIG_IN and COMP_IN as shown

in Fig. 9. Typical waveforms for the PC2 loop locked at fo are shown in Fig. 10.

When the SIG_IN and COMP_IN frequencies are equal but the phase of SIG_IN leads that

of COMP_IN, the p-type output driver at PC2_OUT is held ‘ON’. The time that it is held 'ON’

corresponds with the phase difference (ΦDEM_OUT). When the phase of SIG_IN lags that of

COMP_IN, the n-type driver is held ‘ON’.

When the SIG_IN frequency is higher than the COMP_IN frequency, the p-type output driver is

held ‘ON’ for most of the input signal cycle time. For the remainder of the cycle time, both n- and

p-type drivers are ‘OFF’ (3-state). If the SIG_IN frequency is lower than the COMP_IN frequency,

the n-type driver is held ‘ON’ for most of the cycle. The voltage at capacitor (C2) of the low-pass

filter, connected to PC2_OUT, varies until the phase and frequency of the signal and comparator

inputs are equal. At this stable point, the voltage on C2 remains constant as the PC2 output is in 3-

state and the VCO_IN input is in a high-impedance state. In this condition, the signal at the phase

comparator pulse output (PCP_OUT) is a HIGH level and can be used for indicating a locked

condition.

Thus for PC2 no phase difference exists between SIG_IN and COMP_IN over the full frequency

range of the VCO. The power dissipation due to the low-pass filter is reduced because both n- and

p-type output drivers are ‘OFF’ for most of the signal input cycle. The PLL lock range for this type of

phase comparator is equal to the capture range and is independent of the low-pass filter. With no

signal present at SIG_IN the VCO adjust, via PC2, to its lowest frequency.

74HC_HCT4046A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 6 August 2019

© Nexperia B.V. 2019. All rights reserved

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