74HC4046APW データシートの表示（PDF） - NXP Semiconductors.

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74HC4046APW

Phase-locked loop with VCO

NXP Semiconductors. 

Nexperia

74HC4046A; 74HCT4046A

Phase-locked loop with VCO

PC3 is fed to the VCO via the low-pass filter and present at the demodulator output at pin

DEM_OUT. The average output from PC3 is the resultant of the phase differences of SIG_IN and

COMP_IN, see Fig. 11. Typical waveforms for the PC3 loop locked at fo are shown in Fig. 12.

The phase-to-output response characteristic of PC3 (Fig. 11) differs from PC2 in that the phase

angle between SIG_IN and COMP_IN varies between 0° and 360°. It is 180° at the center

frequency. Also PC3 gives a greater voltage swing than PC2 for input phase differences. As a

result, the ripple content of the VCO input signal is higher. The PLL lock range for this type of

phase comparator and the capture range are dependent on the low-pass filter. With no signal

present at SIG_IN, the VCO adjusts to its lowest frequency via PC3.

VCC

VDEM_OUT

(V)

1/2 VCC

0

0

π

ØDEM_OUT(rad)

2π

aaa-020210

Fig. 11. Phase comparator 3; average output voltage as a function of input phase

difference

SIG_IN

COMP_IN

VCO_OUT

PC3_OUT

VCO_IN

VCC

GND

aaa-020211

Fig. 12. Typical waveforms for PLL using phase comparator 3; loop-locked at f0

74HC_HCT4046A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 6 August 2019

© Nexperia B.V. 2019. All rights reserved

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