4017B データシートの表示（PDF） - Philips Electronics
部品番号
コンポーネント説明
メーカー
4017B Datasheet PDF : 8 Pages
| |||
Philips Semiconductors
5-stage Johnson counter
Product specification
HEF4017B
MSI
Output transition
times
HIGH to LOW
LOW to HIGH
VDD
V
SYMBOL MIN.
TYP.
5
60
10 tTHL
30
15
20
5
60
10 tTLH
30
15
20
MAX.
TYPICAL EXTRAPOLATION
FORMULA
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL MIN.
TYP.
Hold times
CP0 →CP1
CP1 → CP0
Minimum clock
pulse width:
CP0 = LOW;
CP1 = HIGH
Minimum MR
pulse width; HIGH
Recovery time
for MR
Maximum clock
pulse frequency
5
10
thold
15
5
10
thold
15
5
10
tWCPL =
tWCPH
15
5
10
tWMRH
15
5
10 tRMR
15
5
10 fmax
15
90
45
40
20
20
10
80
40
40
20
30
10
80
40
40
20
30
15
50
25
30
15
20
10
60
30
30
15
20
10
6
12
12
24
15
30
MAX.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
see also waveforms
Figs 4 and 5
VDD
V
Dynamic power
5
dissipation per
10
package (P)
15
TYPICAL FORMULA FOR P (µW)
500 fi + ∑ (foCL) × VDD2
2200 fi + ∑ (foCL) × VDD2
6000 fi + ∑ (foCL) × VDD2
where
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
5
Share Link: 