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AT90PWM2(2005) データシートの表示(PDF) - Atmel Corporation

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AT90PWM2 Datasheet PDF : 365 Pages
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Overview
Block Diagram
The AT90PWM2/3 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the AT90PWM2/3 achieves throughputs approaching 1 MIPS per MHz allowing the sys-
tem designer to optimize power consumption versus processing speed.
Figure 4. Block Diagram
8Kx8 Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Data Bus 8-bit
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Data
SRAM
512 bytes
EEPROM
512 bytes
I/O Lines
Interrupt
Unit
SPI
Unit
Watchdog
Timer
3 Analog
Comparators
DALI USART
Timer 0
Timer 1
ADC
DAC
PSC 2/1/0
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The AT90PWM2/3 provides the following features: 8K bytes of In-System Programma-
ble Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 53
general purpose I/O lines, 32 general purpose working registers,three Power Stage
Controllers, two flexible Timer/Counters with compare modes and PWM, one USART
8 AT90PWM2/3
4317B–AVR–02/05

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