CYUSB3031(2013) データシートの表示（PDF） - Cypress Semiconductor
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CYUSB3031 Datasheet PDF : 50 Pages
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CYUSB3035
The MMC slave interface features are as follows:
■ Interface operations are compatible with the MMC-System
Specification, MMCA Technical Committee, Version 4.2.
■ Supports booting from an eMMC device connected to the
S-Port. This feature is supported for eMMC devices operating
up to 52-MHz SDR.
■ Supports PMMC interface voltage ranges of 1.7 V to 1.95 V
and 2.7 V to 3.6 V.
■ Supports open drain (both drive and receive open drain signals)
on CMD pin to allow GO_IRQ_STATE (CMD40) for PMMC.
■ Interface clock-frequency range: 0 to 52 MHz.
■ Supports 1-bit, 4-bit, or 8-bit mode of operation. This
configuration is determined by the MMC initialization
procedure.
■ FX3S responds to standard initialization phase commands as
specified for the MMC 4.2 slave device.
■ PMMC mode MMC 4.2 command classes: Class 0 (Basic),
Class 2 (Block read), and Class 4 (Block write), Class 9 (I/O).
FX3S supports the following PMMC commands:
■ Class 0: Basic
CMD0, CMD1, CMD2, CMD3, CMD4, CMD6, CMD7, CMD8,
CMD9, CMD10, CMD12, CMD13, CMD15, CMD19, CMD5
(wakeup support)
■ Class 2: Block Read
CMD16, CMD17, CMD18, CMD23
■ Class 4: Block Write
CMD16, CMD23, CMD24, CMD25
■ Class 9: I-O
CMD39, CMD40
CPU
FX3S has an on-chip 32-bit, 200-MHz ARM926EJ-S core CPU.
The core has direct access to 16 kB of Instruction Tightly
Coupled Memory (TCM) and 8 kB of Data TCM. The
ARM926EJ-S core provides a JTAG interface for firmware
debugging.
FX3S offers the following advantages:
■ Integrates 512 KB of embedded SRAM for code and data and
8 KB of Instruction cache and Data cache.
■ Implements efficient and flexible DMA connectivity between the
various peripherals (such as, USB, GPIF II, I2S, SPI, UART),
requiring firmware only to configure data accesses between
peripherals, which are then managed by the DMA fabric.
■ Allows easy application development on industry-standard
development tools for ARM926EJ-S.
Examples of the FX3S firmware are available with the Cypress
EZ-USB FX3S Development Kit. Software APIs that can be
ported to an external processor are available with the Cypress
EZ-USB FX3S Software Development Kit.
Storage Port (S-Port)
FX3S has two independent storage ports (S0-Port and S1-Port).
Both storage ports support the following specifications:
■ MMC-system specification, MMCA Technical Committee,
Version 4.41
■ SD specification, Version 3.0
■ SDIO host controller compliant with SDIO Specification Version
2.00 (Jan.30, 2007)
Both storage ports support the following features:
SD/MMC Clock Stop
FX3S supports the stop clock feature, which can save power if
the internal buffer is full when receiving data from the
SD/MMC/SDIO.
SD_CLK Output Clock Stop
During the data transfer, the SD_CLK clock can be enabled (on)
or disabled (stopped) at any time by the internal flow control
mechanism.
SD_CLK output frequency is dynamically configurable using a
clock divisor from a system clock. The clock choice for the divisor
is user-configurable through a register. For example, the
following frequencies may be configured:
■ 400 kHz – For the SD/MMC card initialization
■ 20 MHz – For a card with 0- to 20-MHz frequency
■ 24 MHz – For a card with 0- to 26-MHz frequency
■ 48 MHz – For a card with 0- to 52-MHz frequency
(48-MHz frequency on SD_CLK is supported when the clock
input to FX3S is 19.2 MHz or 38.4 MHz)
■ 52 MHz – For a card with 0- to 52-MHz frequency
(52-MHz frequency on SD_CLK is supported when the clock
input to FX3S is 26 MHz or 52 MHz)
■ 100 MHz – For a card with 0- to 100-MHz frequency
If the DDR mode is selected, data is clocked on both the rising
and falling edge of the SD clock. DDR clocks run up to 52 MHz.
Card Insertion and Removal Detection
FX3S supports the two-card insertion and removal detection
mechanisms.
■ Use of SD_D[3] data: During system design, this signal must
have an external 470-kΩ pull-down resistor connected to
SD_D[3]. SD cards have an internal 10-kΩ pull-up resistor.
When the card is inserted or removed from the SD/MMC
connector, the voltage level at the SD_D[3] pin changes and
triggers an interrupt to the CPU. The older generations of MMC
cards do not support this card detection mechanism.
■ Use of the S0/S1_INS pin: Some SD/MMC connectors facilitate
a micro switch for card insertion/removal detection. This micro
switch can be connected to S0/S1_INS. When the card is
inserted or removed from the SD/MMC connector, it turns the
micro switch on and off. This changes the voltage level at the
pin that triggers the interrupt to the CPU. The card-detect micro
switch polarity is assumed to be the same as the write-protect
Document Number: 001-84160 Rev. *B
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