AD1856RZ-REEL7 データシートの表示（PDF） - Analog Devices

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AD1856RZ-REEL7

16-Bit PCM Audio DAC

Analog Devices 

Data Sheet

AD1856

DIGITAL CIRCUIT CONSIDERATIONS

INPUT DATA

Data is transmitted to the AD1856 in a bit stream composed

of 16-bit words with a serial, MSB first format. Three signals

must be present to achieve proper operation: the data, clock,

and latch enable signals. Input data bits are clocked into the

input register on the rising edge of the clock signal. The LSB is

clocked in on the 16th clock pulse. When all data bits are loaded,

a low-going latch enable pulse updates the DAC input. Figure 8

illustrates the general signal requirements for data transfer for

the AD1856.

CLK

Figure 9 provides the specific timing requirements that must be

met for the data transfer to be accomplished properly.

The input pins of the AD1856 are both TTL and 5 V CMOS

compatible, independent of the power supply voltages used.

The input requirements illustrated in Figure 8 and Figure 9

are compatible with the data outputs provided by popular DSP

filter chips used in digital audio playback systems. The AD1856

input clock can run at a 10 MHz rate. This clock rate allows data

transfer rates for 2×, 4×, or 8× oversampling reconstruction. The

Applications of the AD1856 PCM Audio DAC section provides

additional guidelines for using the AD1856 with various DSP

filter chips.

M

L

DATA S

S

B

B

LE

Figure 8. Signal Requirements of the AD1856

CLK

LATCH

ENABLE (LE)

DATA

>100ns

>30ns >30ns

>60ns >15ns

>40ns >40ns

>50ns

>15ns >15ns

INTERNAL DAC INPUT REGISTER

UPDATED WITH 16 MOST RECENT BITS

MSB

1ST BIT

2ND BIT

LSB

16TH BIT

NEXT

WORD

BITS CLOCKED INTO

SHIFT REGISTER

Figure 9. Timing Relationships of Input Signals

Rev. C | Page 11 of 16

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