T24C16A データシートの表示（PDF） - Unspecified

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T24C16A

T24C0XA, T24C02A EEPROM

Unspecified 







must precede any other command (see to Figure 2 on page 5).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a

read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 2 on

page 5).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM

in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This

happens during the ninth clock cycle.

STANDBY MODE: The T24C02A/T24C04A/T24C08A/T24C16A features a low-power standby

mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the

completion of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part

can be reset by following these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition.

Figure 1: Data Validity

Figure 2: Start and Stop Definition

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