MPU-9150 Product Specification
Document Number: PS-MPU-9150A-00
Revision: 4.3
Release Date: 9/18/2013
10.3 Logic Levels Diagram
The figure below depicts a sample circuit with a third party pressure sensor attached to the auxiliary I2C bus.
It shows logic levels and voltage connections. Note: Actual configuration will depend on the auxiliary sensors
used.
VLOGIC
VDD
(0V - VLOGIC)
VLOGIC
SYSTEM BUS
VDD_IO
System
Processor
IO
(0V - VLOGIC)
(0V - VLOGIC)
VDD
(0V - VLOGIC)
INT
CLKIN
FSYNC
SDA
SCL
(0V - VLOGIC)
(0V - VLOGIC)
VLOGIC
MPU-9150
VLOGIC
(0V, VLOGIC)
AD0
ES_DA
ES_CL
0V - VDD
0V - VDD
VDD
VLOGIC
SDA
SCL
VDD
INT 1
INT 2
3rd Party ADDR
Pressure sensor
(0V - VLOGIC)
(0V - VLOGIC)
0V - VDD
I/O Levels and Connections
Notes:
1. The IO voltage levels of ES_DA and ES_CL are set relative to VDD.
2. Third-party auxiliary device logic levels are referenced to VDD. Setting INT1 and INT2 to open drain
configuration provides voltage compatibility when VDD ≠ VLOGIC. When VDD = VLOGIC, INT1 and
INT2 may be set to push-pull outputs, and external pull-up resistors are not needed.
3. All other MPU-9150 logic IO is always referenced to VLOGIC.
Proprietary and Confidential
37 of 50