S34ML01G2 データシートの表示（PDF） - Spansion Inc.
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S34ML01G2 Datasheet PDF : 79 Pages
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Data Sheet
1.6 Addressing
1.6.1 S34ML01G2
Table 1.3 Address Cycle Map — 1 Gb Device
Bus Cycle I/O [15:8] (5)
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
x8
1st / Col. Add.1
—
A0 (CA0) A1 (CA1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)
2nd / Col. Add. 2
—
A8 (CA8) A9 (CA9) A10 (CA10) A11 (CA11) Low
Low
Low
Low
3rd / Row Add. 1
—
A12 (PA0) A13 (PA1) A14 (PA2) A15 (PA3) A16 (PA4) A17 (PA5) A18 (BA0) A19 (BA1)
4th / Row Add. 2
—
A20 (BA2) A21 (BA3) A22 (BA4) A23 (BA5) A24 (BA6) A25 (BA7) A26 (BA8) A27 (BA9)
x16
1st / Col. Add.1
Low
A0 (CA0) A1 (CA1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)
2nd / Col. Add. 2
Low
A8 (CA8) A9 (CA9) A10 (CA10)
Low
Low
Low
Low
Low
3rd / Row Add. 1
Low
A11 (PA0) A12 (PA1) A13 (PA2) A14 (PA3) A15 (PA4) A16 (PA5) A17 (BA0) A18 (BA1)
4th / Row Add. 2
Low
A19 (BA2) A20 (BA3) A21 (BA4) A22 (BA5) A23 (BA6) A24 (BA7) A25 (BA8) A26 (BA9)
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. BAx = Block Address bit.
4. Block address concatenated with page address = actual page address, also known as the row address.
5. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the x8 address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18 - A27: block address
For the x16 address bits, the following rules apply:
A0 - A10: column address in the page
A11 - A16: page address in the block
A17 - A26: block address
September 5, 2014 S34ML01G2_04G2_10
Spansion® SLC NAND Flash Memory for Embedded
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