HMT325S6CFR8C データシートの表示（PDF） - Hynix Semiconductor

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HMT325S6CFR8C

204pin DDR3 SDRAM SODIMM

Hynix Semiconductor 

Single Ended Output Slew Rate

When the Reference load for timing measurements, output slew rate for falling and rising edges is defined

and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and figure below.

Single-ended Output slew Rate Definition

Description

Measured

From

To

Defined by

Single-ended output slew rate for rising edge

Single-ended output slew rate for falling edge

Notes:

VOL(AC)

VOH(AC)

VOH(AC)

VOL(AC)

[VOH(AC)-VOL(AC)] / DeltaTRse

[VOH(AC)-VOL(AC)] / DeltaTFse

1. Output slew rate is verified by design and characterisation, and may not be subject to production test.

Delta TFse

Delta TRse

VOH(AC)

V∏

VOl(AC)

Single Ended Output slew Rate Definition

Output Slew Rate (single-ended)

Parameter

Symbol

DDR3-800

Min Max

DDR3-1066

Min Max

DDR3-1333

Min Max

DDR3-1600

Units

Min Max

Single-ended Output Slew Rate SRQse 2.5

5

2.5

5

2.5

5

2.5

5 V/ns

Description: SR; Slew Rate

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

se: Single-ended Signals

For Ron = RZQ/7 setting

Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.

Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high

to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).

Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high

to low or low to high) while all remaining DQ signals in the same byte lane switching into the opposite direction (i.e. from

low to high of high to low respectively). For the remaining DQ signal switching in to the opposite direction, the regular

maximum limite of 5 V/ns applies.

Rev. 1.0/Sep. 2012

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