LE25FS406FQ データシートの表示（PDF） - SANYO -> Panasonic

部品番号

コンポーネント説明

メーカー

LE25FS406FQ

4M-bit (512K×8) Serial Flash Memory

SANYO -> Panasonic 

Figure 2 Block Diagram

LE25FS406

ADDRESS

BUFFERS

&

LATCHES

X-

DECODER

4M Bit

Flash EEPROM

Cell Array

Y-DECODER

CONTROL

LOGIC

I/O BUFFERS

&

DATA LATCHES

SERIAL INTERFACE

Table 1 Pin Description

Symbol

SCK

Pin Name

Serial clock

SI

Serial data input

SO

Serial data output

CS

Chip select

WP

HOLD

VDD

VSS

Write protect

Hold

Power supply

Ground

CS SCK SI SO WP HOLD

Description

This pin controls the data input/output timing.

The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is

output synchronized to the falling edge of the serial clock.

The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the

serial clock.

The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock.

The device becomes active when the logic level of this pin is low; it is deselected and placed in standby

status when the logic level of the pin is high.

The status register write protect (SRWP) takes effect when the logic level of this pin is low.

Serial communication is suspended when the logic level of this pin is low.

This pin supplies the 1.65 to 2.10V supply voltage.

This pin supplies the 0V supply voltage.

No.A1577-3/22

Share Link: