SPT9687 データシートの表示（PDF） - Fairchild Semiconductor
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SPT9687 Datasheet PDF : 8 Pages
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ELECTRICAL SPECIFICATIONS
T A = +25 °C, VCC = +5.0 V, VEE = -5.20 V, RL = 50 Ohm, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
AC ELECTRICAL CHARACTERISTICS2
MIN
SPT9687
TYP
Latch to Output Delay
50 mV OD
IV
Latch Pulse Width
V
2
Latch Hold Time
IV
Rise Time
20% to 80%
V
1.2
Fall Time
20% to 80%
V
1.2
1RS = Source impedance.
2100 mV input step.
TEST LEVEL CODES
TEST LEVEL TEST PROCEDURE
MAX
UNITS
3
ns
ns
0.5
ns
ns
ns
All electrical characteristics are subject to the
I
following conditions:
II
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
III
cates the specific device testing actually per-
IV
formed during production and Quality Assur-
ance inspection. Any blank section in the data
V
column indicates that the specification is not
tested at the specified condition.
VI
Unless otherwise noted, all tests are pulsed
tests; therefore, TJ = TC = TA.
100% production tested at the specified temperature.
100% production tested at TA=25 °C, and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
Figure 1 - Timing Diagram
LATCH ENABLE
LATCH ENABLE
DIFFERENTIAL
INPUT VOLTAGE
OUTPUT Q
tH
tS
VOD
tpdL
tpL
t pLOH
50%
VREF ± VOS
50%
OUTPUT Q
tpdH
tpLOL
50%
VIN+ = 100 mV (p-p), VOD = 50 mV
The set-up and hold times are a measure of the time required for an input signal to propagate through the
first stage of the comparator to reach the latching circuitry. Input signals occurring before ts will be detected
and held; those occurring after tH will not be detected. Changes between ts and tH may not be detected.
SPT9687
3
3/21/97
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