SPT9687 データシートの表示（PDF） - Fairchild Semiconductor
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SPT9687 Datasheet PDF : 8 Pages
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Figure 3 - Typical Interface Circuit
VCC GND VEE
.1 µF
Noninverting
Input
VIN
VRef
Inverting
Input
+
Q Output
-
Q Output
LE
LE
ECL
RL
50 Ω
RL
50 Ω
.1 µF
-2 V
= Represents line termination.
Figure 5 - Equivalent Input Circuit
VCC
C IN
1 pF
RIN
V IN
100 Ω
RIN
VIN
100 Ω
VR2
VR1
V EE
Q3
R1
C IN
1 pF
Q1
Q4
R2
Q7
Q5
Q9
Q11
V PRE
V PRE
Q2
R3
Q6
R4
Q8
R5
Q10
Q12
R6
R7
Figure 4 - Typical Interface With Hysteresis
VCC GND VEE
VO
Noninverting
Input
VIN
VREF
Inverting
Input
+
-
LE
-5.2 V
VLE
300 Ω
.1 µF
VIN
LE
VLE
RL
50 Ω
Q OUTPUT
Q OUTPUT
RL
50 Ω
-2 V
300 Ω
.1 µF
-5.2 V
100 Ω
0.1 µF
100 Ω
Hysteresis is obtained by applying a DC bias to the LE pin.
VLE = -1.3 V ±100 mV, VLE = -1.3 V.
Represents line termination.
Figure 6 - AC Test Fixture
V+
IN
MONITOR
VCC
(+5.0 V)
GND
15 µF
L1 6
L3
0.1 µF
50
6
50
6
V+
IN
SEMI-
RIGID
6
V-
SEMI-
IN
RIGID
L2
100
V+
+
Q
DUT 4
Q
-
V-
LE
100
50
SEMI
RIGID
6
SEMI
RIGID
V+
OUT
VOUT-
LE
100
50
0.1 µF
L2
0.1 µF
0.1 µF
50
SAMPLING
SCOPE
100
100
50
L1
6
6
50
L1
6
6
15 µF
15 µF
TANT
- ++-
LE
LE
MONITOR
LE
LE
VEE
V pD
MONITOR
(-5.2 V)
(-4.0 V)
Figure 7 - Output Circuit
Q Output
R7
240 Ω
Q23
V1
Q21
R8
240 Ω
Q24
Q22
V2
Q Output
Figure 8 - Test Load
Rz
50 Ω
RL
100 Ω
50 Ω Coax
RZ
100 Ω
4.5 mA
Vpd
(-4.0 V)
SPT9687
5
3/21/97
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