MPC8270CVVB データシートの表示（PDF） - Freescale Semiconductor

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MPC8270CVVB

PowerQUICC II Family Hardware Specifications

Freescale Semiconductor 

Overview

This figure shows the block diagram of the SoC. Shaded portions are SoC-specific; see the notes below

the figure.

G2_LE Core

16 KB

I-Cache

I-MMU

16 KB

D-Cache

D-MMU

Timers

Parallel I/O

Baud Rate

Generators

Communication Processor Module (CPM)

Interrupt

Controller

32 KB

Instruction

RAM

32 KB

Data

RAM

32-bit RISC Microcontroller

and Program ROM

MicIMroAco1de

Serial

DMAs

4 Virtual

IDMAs

System Interface Unit

(SIU)

Bus Interface Unit

60x-to-PCI

Bridge

60x-to-Local

Bridge

Memory Controller

Clock Counter

System Functions

60x Bus

PCI Bus

32 bits, up to 66 MHz

or

Local Bus

32 bits, up to 100 MHz

MCC11 MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4/ SMC1 SMC2 SPI

I2C

USB

TC Layer Hardware1

Time Slot Assigner

Serial Interface2

8 TDM Ports2

3 MII or RMII

Ports

2 UTOPIA

Ports3

Non-Multiplexed

I/O

Notes:

1 MPC8280 only (not on MPC8270, the VR package, nor the ZQ package)

2 MPC8280 has 2 serial interface (SI) blocks and 8 TDM ports. MPC8270 and the VR and ZQ packages have

only 1 SI block and 4 TDM ports (TDM2[A–D]).

3 MPC8280, MPC8275VR, MPC8275ZQ only (not on MPC8270, MPC8270VR, nor MPC8270ZQ)

Figure 1. SoC Block Diagram

1.1 Features

The major features of the SoC are as follows:

• Dual-issue integer (G2_LE) core

— A core version of the EC603e microprocessor

— System core microprocessor supporting frequencies of 166–450 MHz

— Separate 16 KB data and instruction caches:

– Four-way set associative

– Physically addressed

– LRU replacement algorithm

— Power Architecture®-compliant memory management unit (MMU)

MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2

Freescale Semiconductor

3

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