XC2735X データシートの表示（PDF） - Infineon Technologies

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XC2735X

16/32-Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family Derivatives / Base Line

Infineon Technologies 

XC2735X

XC2000 Family Derivatives / Base Line

Functional Description

3.5

Interrupt System

With a minimum interrupt response time of 7/111) CPU clocks (in the case of internal

program execution), the XC2735X can react quickly to the occurrence of non-

deterministic events.

The architecture of the XC2735X supports several mechanisms for fast and flexible

response to service requests; these can be generated from various sources internal or

external to the microcontroller. Any of these interrupt requests can be programmed to be

serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC).

Where in a standard interrupt service the current program execution is suspended and

a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the

current CPU activity to perform a PEC service. A PEC service implies a single byte or

word data transfer between any two memory locations with an additional increment of

either the PEC source pointer, the destination pointer, or both. An individual PEC

transfer counter is implicitly decremented for each PEC service except when performing

in the continuous transfer mode. When this counter reaches zero, a standard interrupt is

performed to the corresponding source-related vector location. PEC services are

particularly well suited to supporting the transmission or reception of blocks of data. The

XC2735X has eight PEC channels, each whith fast interrupt-driven data transfer

capabilities.

Each of the possible interrupt nodes has a separate control register containing an

interrupt request flag, an interrupt enable flag and an interrupt priority bitfield. Each node

can be programmed by its related register to one of sixteen interrupt priority levels. Once

accepted by the CPU, an interrupt service can only be interrupted by a higher-priority

service request. For standard interrupt processing, each possible interrupt node has a

dedicated vector location.

Fast external interrupt inputs can service external interrupts with high-precision

requirements. These fast interrupt inputs feature programmable edge detection (rising

edge, falling edge, or both edges).

Software interrupts are supported by the ‘TRAP’ instruction in combination with an

individual trap (interrupt) number.

Table 7 shows all of the possible XC2735X interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers.

Note: Interrupt nodes which are not assigned to peripherals (unassigned nodes) may be

used to generate software-controlled interrupt requests by setting the respective

interrupt request bit (xIR).

1) Depending if the jump cache is used or not.

Data Sheet

30

V2.0, 2009-03

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