TEA2164S データシートの表示（PDF） - STMicroelectronics
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TEA2164S Datasheet PDF : 16 Pages
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TEA2164S
II - GENERAL DESCRIPTION (continued)
Figure 8 : Overvoltages Lock-out
VCC > VCC(Max.)
IC > ICM2
S
Q
1 : discharge
RR
BURST
OSCILLATOR
VCC STOP
CROSSING
S
OUTPUT
FLIP-FLOP
R
Synchro ”off”
Figure 9 : Long Duration Overload Monitoring Circuit
I3 ch. +
I3 disch.
S
QR
1 : VCM3 detection before
negative pulse occurence
sawtooth return
C2
3
I3 disch.
VC2
VCC < 4.8V
S
RQ
I3 dischr. = 0 in burst mode
Figure 10 : Long Duration Overload Detection
ICM1
Collector
Current
Envelop
0
Capacitor C2
VC2
Voltage
0
TEA2164S
VCC Voltage
0
Overload
VCC(START)
VCC(STOP)
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