ISPLS1024/883 データシートの表示（PDF） - Lattice Semiconductor

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ISPLS1024/883

In-System Programmable High Density PLD

Lattice Semiconductor 

Specifications ispLSI 1024/883

Functional Block Diagram

Figure 1.ispLSI 1024/883 Functional Block Diagram

RESET

Generic

Logic Blocks

(GLBs)

I/O 0

I/O 1

A0

I/O 2

I/O 3

A1

I/O 4

A2

I/O 5

I/O 6

I/O 7

A3

I/O 8

A4

I/O 9

I/O 10

I/O 11

A5

I/O 12

A6

I/O 13

I/O 14

I/O 15

A7

Global

Routing

Pool

(GRP)

SDI/IN 0

SDO/IN 1

B0 B1 B2 B3 B4 B5 B6 B7

Megablock

ispEN

SCLK/IN 2

MODE/IN 3

Output Routing Pool (ORP)

Input Bus

I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

IN 5

IN 4

I/O 47

C7

I/O 46

I/O 45

C6

I/O 44

I/O 43

C5

I/O 42

I/O 41

C4

I/O 40

C3

I/O 39

I/O 38

I/O 37

C2

I/O 36

C1

I/O 35

I/O 34

I/O 33

C0

I/O 32

Clock

Distribution

Network

CLK 0

CLK 1

CLK 2

IOCLK 0

IOCLK 1

YYYY

0123

0139D_1024.eps

The device also has 48 I/O cells, each of which is directly

connected to an I/O pin. Each I/O cell can be individually

programmed to be a combinatorial input, registered in-

put, latched input, output or bi-directional

I/O pin with 3-state control. Additionally, all outputs are

polarity selectable, active high or active low. The signal

levels are TTL compatible voltages and the output drivers

can source 4 mA or sink 8 mA.

Eight GLBs, 16 I/O cells, two dedicated inputs and one

ORP are connected together to make a Megablock (see

figure 1). The outputs of the eight GLBs are connected

to a set of 16 universal I/O cells by the ORP. The I/O cells

within the Megablock also share a common Output

Enable (OE) signal. The ispLSI 1024/883 device con-

tains three of these Megablocks.

The GRP has as its inputs the outputs from all of the GLBs

and all of the inputs from the bi-directional I/O cells. All of

these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 1024/883 device are selected using

the Clock Distribution Network. Four dedicated clock pins

(Y0, Y1, Y2 and Y3) are brought into the distribution

network, and five clock outputs (CLK 0, CLK 1, CLK 2,

IOCLK 0 and IOCLK 1) are provided to route clocks to the

GLBs and I/O cells. The Clock Distribution Network can

also be driven from a special clock GLB (B4 on the ispLSI

1024/883 device). The logic of this GLB allows the user

to create an internal clock from a combination of internal

signals within the device.

2

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