DSPIC33FJ06GS101 データシートの表示（PDF） - Microchip Technology

部品番号

コンポーネント説明

メーカー

DSPIC33FJ06GS101

High-Performance, 16-bit Digital Signal Controllers

Microchip Technology 

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Buffer PPS

Type Type Capable

Description

CMP1A

CMP1B

CMP1C

CMP1D

CMP2A

CMP2B

CMP2C

CMP2D

CMP3A

CMP3B

CMP3C

CMP3D

CMP4A

CMP4B

CMP4C

CMP4D

I

Analog No Comparator 1 Channel A

I

Analog No Comparator 1 Channel B

I

Analog No Comparator 1 Channel C

I

Analog No Comparator 1 Channel D

I

Analog No Comparator 2 Channel A

I

Analog No Comparator 2 Channel B

I

Analog No Comparator 2 Channel C

I

Analog No Comparator 2 Channel D

I

Analog No Comparator 3 Channel A

I

Analog No Comparator 3 Channel B

I

Analog No Comparator 3 Channel C

I

Analog No Comparator 3 Channel D

I

Analog No Comparator 4 Channel A

I

Analog No Comparator 4 Channel B

I

Analog No Comparator 4 Channel C

I

Analog No Comparator 4 Channel D

DACOUT

O

—

No DAC output voltage

ACMP1-ACMP4 O

—

Yes DAC trigger to PWM module

EXTREF

I

Analog No External voltage reference input for the reference DACs

REFCLKO

O

—

Yes REFCLKO output signal is a postscaled derivative of the system

clock

FLT1-FLT8

I

SYNCI1-SYNCI2 I

SYNCO1

O

PWM1L

O

PWM1H

O

PWM2L

O

PWM2H

O

PWM3L

O

PWM3H

O

PWM4L

O

PWM4H

O

ST

Yes Fault Inputs to PWM module

ST

Yes External synchronization signal to PWM Master Time Base

—

Yes PWM master time base for external device synchronization

—

No PWM1 low output

—

No PWM1 high output

—

No PWM2 low output

—

No PWM2 high output

—

No PWM3 low output

—

No PWM3 high output

—

Yes PWM4 low output

—

Yes PWM4 high output

PGED1

PGEC1

PGED2

PGEC2

PGED3

PGEC3

I/O

ST

I

ST

I/O

ST

I

ST

I/O

ST

I

ST

No Data I/O pin for programming/debugging communication Channel 1

No Clock input pin for programming/debugging communication

Channel 1

No Data I/O pin for programming/debugging communication Channel 2

No Clock input pin for programming/debugging communication

Channel 2

No Data I/O pin for programming/debugging communication Channel 3

No Clock input pin for programming/debugging communication

Channel 3

MCLR

I/P

ST

No Master Clear (Reset) input. This pin is an active-low Reset to the

device.

AVDD

P

P

No Positive supply for analog modules. This pin must be connected at

all times.

AVSS

P

P

No Ground reference for analog modules

VDD

P

—

No Positive supply for peripheral logic and I/O pins

VCAP/VDDCORE

P

—

No CPU logic filter capacitor connection

VSS

P

—

No Ground reference for logic and I/O pins

Legend: CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

TTL = Transistor-Transistor Logic

Analog = Analog input I = Input

P = Power

O = Output

PPS = Peripheral Pin Select

DS70318D-page 18

Preliminary

© 2009 Microchip Technology Inc.

Share Link: