BD82B65 データシートの表示（PDF） - Intel

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BD82B65

Intel® 6 Series Chipset and Intel® C200 Series Chipset

Intel 

Contents

1 Introduction ............................................................................................................ 41

1.1 About This Manual ............................................................................................. 41

1.2 Overview ......................................................................................................... 44

1.2.1

Capability Overview............................................................................. 45

1.3 Intel® 6 Series Chipset and Intel® C200 Series Chipset SKU Definition ..................... 51

2 Signal Description ................................................................................................... 55

2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 57

2.2 PCI Express* .................................................................................................... 57

2.3 PCI Interface .................................................................................................... 58

2.4 Serial ATA Interface........................................................................................... 60

2.5 LPC Interface.................................................................................................... 63

2.6 Interrupt Interface ............................................................................................ 63

2.7 USB Interface ................................................................................................... 64

2.8 Power Management Interface.............................................................................. 65

2.9 Processor Interface............................................................................................ 69

2.10 SMBus Interface................................................................................................ 69

2.11 System Management Interface............................................................................ 69

2.12 Real Time Clock Interface ................................................................................... 70

2.13 Miscellaneous Signals ........................................................................................ 70

2.14 Intel® High Definition Audio Link ......................................................................... 72

2.15 Controller Link .................................................................................................. 73

2.16 Serial Peripheral Interface (SPI) .......................................................................... 73

2.17 Thermal Signals ................................................................................................ 73

2.18 Testability Signals ............................................................................................. 74

2.19 Clock Signals .................................................................................................... 74

2.20 LVDS Signals .................................................................................................... 77

2.21 Analog Display /VGA DAC Signals ........................................................................ 78

2.22 Intel® Flexible Display Interface (Intel® FDI) ........................................................ 78

2.23 Digital Display Signals........................................................................................ 79

2.24 General Purpose I/O Signals ............................................................................... 82

2.25 Manageability Signals ........................................................................................ 86

2.26 Power and Ground Signals .................................................................................. 87

2.27 Pin Straps ........................................................................................................ 89

2.28 External RTC Circuitry ........................................................................................ 92

3 PCH in PtateSs......................................................................................................... 93

3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 93

3.2 Output and I/O Signals Planes and States............................................................. 95

3.3 Power Planes for Input Signals .......................................................................... 107

4 PCH and System Clocks ......................................................................................... 113

4.1 Platform Clocking Requirements ........................................................................ 113

4.2 Functional Blocks ............................................................................................ 116

4.3 Clock Configuration Access Overview ................................................................. 117

4.4 Straps Related to Clock Configuration ................................................................ 117

5 Functional Description ........................................................................................... 119

5.1 DMI-to-PCI Bridge (D30:F0) ............................................................................. 119

5.1.1

PCI Bus Interface.............................................................................. 119

5.1.2

PCI Bridge As an Initiator................................................................... 120

5.1.2.1 Memory Reads and Writes .................................................. 120

5.1.2.2 I/O Reads and Writes ......................................................... 120

5.1.2.3 Configuration Reads and Writes ........................................... 120

5.1.2.4 Locked Cycles ................................................................... 120

5.1.2.5 Target / Master Aborts ....................................................... 120

5.1.2.6 Secondary Master Latency Timer ......................................... 120

5.1.2.7 Dual Address Cycle (DAC)................................................... 121

5.1.2.8 Memory and I/O Decode to PCI ........................................... 121

5.1.3

Parity Error Detection and Generation.................................................. 121

5.1.4

PCIRST# ......................................................................................... 122

5.1.5

Peer Cycles ...................................................................................... 122

Datasheet

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