BD82B65 データシートの表示（PDF） - Intel
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BD82B65 Datasheet PDF : 934 Pages
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5.17
5.18
5.19
5.20
5.21
5.16.9.2 Power State Transitions ...................................................... 204
5.16.9.3 SMI Trapping (APM) ........................................................... 205
5.16.10 SATA Device Presence ....................................................................... 205
5.16.11 SATA LED ........................................................................................ 206
5.16.12 AHCI Operation ................................................................................ 206
5.16.13 SGPIO Signals .................................................................................. 206
5.16.13.1 Mechanism ....................................................................... 206
5.16.13.2 Message Format ................................................................ 207
5.16.13.3 LED Message Type ............................................................. 208
5.16.13.4 SGPIO Waveform............................................................... 209
5.16.14 External SATA .................................................................................. 210
High Precision Event Timers.............................................................................. 210
5.17.1 Timer Accuracy................................................................................. 210
5.17.2 Interrupt Mapping ............................................................................. 211
5.17.3 Periodic versus Non-Periodic Modes ..................................................... 212
5.17.4 Enabling the Timers .......................................................................... 212
5.17.5 Interrupt Levels ................................................................................ 213
5.17.6 Handling Interrupts ........................................................................... 213
5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .......................... 213
USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 214
5.18.1 EHC Initialization .............................................................................. 214
5.18.1.1 BIOS Initialization.............................................................. 214
5.18.1.2 Driver Initialization ............................................................ 214
5.18.1.3 EHC Resets ....................................................................... 214
5.18.2 Data Structures in Main Memory ......................................................... 214
5.18.3 USB 2.0 Enhanced Host Controller DMA ............................................... 215
5.18.4 Data Encoding and Bit Stuffing ........................................................... 215
5.18.5 Packet Formats................................................................................. 215
5.18.6 USB 2.0 Interrupts and Error Conditions .............................................. 215
5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads ........................... 216
5.18.7 USB 2.0 Power Management............................................................... 216
5.18.7.1 Pause Feature ................................................................... 216
5.18.7.2 Suspend Feature ............................................................... 216
5.18.7.3 ACPI Device States ............................................................ 216
5.18.7.4 ACPI System States ........................................................... 217
5.18.8 USB 2.0 Legacy Keyboard Operation.................................................... 217
5.18.9 USB 2.0 Based Debug Port ................................................................. 217
5.18.9.1 Theory of Operation .......................................................... 218
5.18.10 EHCI Caching ................................................................................... 222
5.18.11 Intel® USB Pre-Fetch Based Pause ...................................................... 222
5.18.12 Function Level Reset Support (FLR) ..................................................... 222
5.18.12.1 FLR Steps ......................................................................... 222
5.18.13 USB Overcurrent Protection ................................................................ 223
Integrated USB 2.0 Rate Matching Hub .............................................................. 224
5.19.1 Overview ......................................................................................... 224
5.19.2 Architecture ..................................................................................... 224
SMBus Controller (D31:F3) ............................................................................... 225
5.20.1 Host Controller ................................................................................. 225
5.20.1.1 Command Protocols ........................................................... 226
5.20.2 Bus Arbitration ................................................................................. 229
5.20.3 Bus Timing....................................................................................... 230
5.20.3.1 Clock Stretching ................................................................ 230
5.20.3.2 Bus Time Out (The PCH as SMBus Master) ............................ 230
5.20.4 Interrupts / SMI# ............................................................................. 230
5.20.5 SMBALERT# ..................................................................................... 231
5.20.6 SMBus CRC Generation and Checking .................................................. 231
5.20.7 SMBus Slave Interface....................................................................... 232
5.20.7.1 Format of Slave Write Cycle ................................................ 233
5.20.7.2 Format of Read Command .................................................. 234
5.20.7.3 Slave Read of RTC Time Bytes ............................................. 236
5.20.7.4 Format of Host Notify Command .......................................... 237
Thermal Management ...................................................................................... 238
5.21.1 Thermal Sensor ................................................................................ 238
5.21.1.1 Internal Thermal Sensor Operation ...................................... 238
5.21.2 PCH Thermal Throttling...................................................................... 239
5.21.3 Thermal Reporting Over System Management Link 1 Interface (SMLink1) . 240
5.21.3.1 Supported Addresses ......................................................... 241
Datasheet
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