BD82B65 データシートの表示（PDF） - Intel
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BD82B65 Datasheet PDF : 934 Pages
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5.27.2
5.27.3
5.27.4
5.27.5
Intel® VT-d Features Supported.......................................................... 276
Support for Function Level Reset (FLR) in PCH ...................................... 277
Virtualization Support for PCH’s IOxAPIC .............................................. 277
Virtualization Support for High Precision Event Timer (HPET) .................. 277
6 Ballout Definition................................................................................................... 279
6.1 Desktop PCH Ballout ........................................................................................ 279
6.2 Mobile PCH Ballout .......................................................................................... 290
6.3 Mobile SFF PCH Ballout .................................................................................... 302
7 Package Information ............................................................................................. 307
7.1 Desktop PCH package ...................................................................................... 307
7.2 Mobile PCH Package......................................................................................... 309
7.3 Mobile SFF PCH Package................................................................................... 311
8 Electrical Characteristics ....................................................................................... 313
8.1 Thermal Specifications ..................................................................................... 313
8.1.1
Desktop Storage Specifications and Thermal Design Power (TDP) ............ 313
8.1.2
Mobile Storage Specifications and Thermal Design Power (TDP) .............. 313
8.2 Absolute Maximum Ratings............................................................................... 314
8.3 PCH Power Supply Range ................................................................................. 315
8.4 General DC Characteristics ............................................................................... 315
8.5 Display DC Characteristics ................................................................................ 328
8.6 AC Characteristics ........................................................................................... 330
8.7 Power Sequencing and Reset Signal Timings ....................................................... 347
8.8 Power Management Timing Diagrams................................................................. 350
8.9 AC Timing Diagrams ........................................................................................ 355
9 Register and Memory Mapping............................................................................... 365
9.1 PCI Devices and Functions................................................................................ 366
9.2 PCI Configuration Map ..................................................................................... 367
9.3 I/O Map ......................................................................................................... 367
9.3.1
Fixed I/O Address Ranges .................................................................. 367
9.3.2
Variable I/O Decode Ranges ............................................................... 370
9.4 Memory Map................................................................................................... 371
9.4.1
Boot-Block Update Scheme ................................................................ 373
10 Chipset Configuration Registers............................................................................. 375
10.1 Chipset Configuration Registers (Memory Space) ................................................. 375
10.1.1 CIR0—Chipset Initialization Register 0 ................................................. 377
10.1.2 RPC—Root Port Configuration Register ................................................. 377
10.1.3 RPFN—Root Port Function Number and Hide for PCI
Express* Root Ports Register .............................................................. 378
10.1.4 FLRSTAT—Function Level Reset Pending Status Register ........................ 379
10.1.5 TRSR—Trap Status Register ............................................................... 380
10.1.6 TRCR—Trapped Cycle Register ............................................................ 380
10.1.7 TWDR—Trapped Write Data Register ................................................... 381
10.1.8 IOTRn—I/O Trap Register (0–3).......................................................... 381
10.1.9 V0CTL—Virtual Channel 0 Resource Control Register.............................. 382
10.1.10 V0STS—Virtual Channel 0 Resource Status Register............................... 382
10.1.11 V1CTL—Virtual Channel 1 Resource Control Register.............................. 383
10.1.12 V1STS—Virtual Channel 1 Resource Status Register............................... 383
10.1.13 REC—Root Error Command Register .................................................... 384
10.1.14 LCAP—Link Capabilities Register ......................................................... 384
10.1.15 LCTL—Link Control Register................................................................ 385
10.1.16 LSTS—Link Status Register ................................................................ 385
10.1.17 DLCTL2—DMI Link Control 2 Register .................................................. 385
10.1.18 DMIC—DMI Control Register ............................................................... 386
10.1.19 TCTL—TCO Configuration Register....................................................... 386
10.1.20 D31IP—Device 31 Interrupt Pin Register .............................................. 387
10.1.21 D30IP—Device 30 Interrupt Pin Register .............................................. 388
10.1.22 D29IP—Device 29 Interrupt Pin Register .............................................. 388
10.1.23 D28IP—Device 28 Interrupt Pin Register .............................................. 388
10.1.24 D27IP—Device 27 Interrupt Pin Register .............................................. 390
10.1.25 D26IP—Device 26 Interrupt Pin Register .............................................. 390
10.1.26 D25IP—Device 25 Interrupt Pin Register .............................................. 390
10.1.27 D22IP—Device 22 Interrupt Pin Register .............................................. 391
10.1.28 D31IR—Device 31 Interrupt Route Register .......................................... 392
Datasheet
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