HD74AC182FPEL データシートの表示（PDF） - Renesas Electronics
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HD74AC182FPEL Datasheet PDF : 7 Pages
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HD74AC182
Cn + x = G0 + P0Cn
Cn + y = G1 + P1G0 + P1P0Cn
Cn + z = G2 + P2G1 + P2P1G0 + P2P1P0Cn
G = G3 + P3G2 + P3P2G1 + P3P2P1G0
P = P3P2P1P0
Also, the HD74AC182/HD74ACT182 can be used with binary ALUs in an active Low or active High input operand
mode. The connections (Figure a) to and from the ALU to the carry lookahead generator are identical in both cases.
Carries are rippled between lookahead blocks. The critical speed path follows the circled numbers. There are several
possible arrangements for the carry interconnects, but all achieve about the same speed. A 28-bit ALU is formed by
dropping the last HD74AC182/HD74ACT182.
Truth Table
Cn
X
L
X
H
X
X
L
X
X
H
X
X
X
L
X
X
X
H
H:
L:
X:
G0
P0
G1
H
H
H
X
L
X
X
L
X
X
H
H
H
H
H
X
H
X
X
L
L
X
X
X
L
X
X
X
X
X
X
H
H
H
H
H
X
H
X
X
X
X
X
L
L
X
X
X
L
X
X
X
X
X
X
H
H
H
X
X
X
X
X
L
L
X
H
X
X
X
L
High Voltage Level
Low Voltage Level
Immaterial
Inputs
P1
G2
H
X
X
X
L
L
X
H
H
H
X
H
X
H
X
L
X
X
L
X
L
X
X
X
X
H
H
H
X
H
X
X
X
L
X
X
L
X
X
H
X
X
L
P2
H
X
X
X
X
L
L
L
X
H
X
X
X
X
L
L
X
X
H
X
L
G3
H
H
H
H
L
X
X
X
P3
H
X
X
X
X
L
L
L
X
X
X
H
L
Cn + x
L
L
H
H
Cn + y
L
L
L
H
H
H
Outputs
Cn + z
G
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
P
H
H
H
H
L
Rev.2.00, Jul.16.2004, page 3 of 6
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