KSZ8081RNA データシートの表示（PDF） - Micrel

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KSZ8081RNA

10Base-T/100Base-TX PHY with RMII Support

Micrel 

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

Strapping Options

Pin Number Pin Name

Type(1) Pin Function

The PHY Address is latched at the de-assertion of reset and is configurable to either

one of the following two values:

15

PHYAD[1:0]

Ipd/O

Pull-up = PHY Address is set to 00011b (0x3h)

Pull-down (default) = PHY Address is set to 00000b (0x0h)

PHY Address bits [4:2] are set to 000 by default.

Auto-Negotiation Enable and SPEED mode

Pull-up (default) = Enable Auto-Negotiation and set 100Mbps Speed

23

ANEN_SPEED Ipu/O

Pull-down = Disable Auto-Negotiation and set 10Mbps Speed

At the de-assertion of reset, this pin value is latched into register 0h bit [12] for Auto-

negotiation enable/disable, register 0h bit [13] for the Speed select, and register 4h

(Auto-Negotiation Advertisement) for the Speed capability support.

Note:

1. Ipu/O = Input with internal pull-up (see “Electrical Characteristics” for value) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (see “Electrical Characteristics” for value) during power-up/reset; output pin otherwise.

The PHYAD[1:0] strap-in pin is latched at the de-assertion of reset. In some systems, the RMII MAC receive input pins

may drive high/low during power-up or reset, and consequently cause the PHYAD[1:0] strap-in pin, a shared pin with the

RMII CRS_DV signal, to be latched to the unintended high/low state. In this case an external pull-up (4.7kΩ) or pull-down

(1.0kΩ) should be added on the PHYAD[1:0] strap-in pin to ensure that the intended value is strapped-in correctly.

February 6, 2014

11

Revision 1.1

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