MX25L8008E データシートの表示（PDF） - Macronix International

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MX25L8008E

8M-BIT [x 1 / x 2] CMOS SERIAL FLASH

Macronix International 

MX25L8008E

DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-

eration.

2. When incorrect command is inputted to this device, it enters standby mode and remains in standby mode until

next CS# falling edge. In standby mode, SO pin of the device is High-Z. The CS# falling time needs to follow

tCHCL spec.

3. When correct command is inputted to this device, it enters active mode and remains in active mode until next

CS# rising edge. The CS# rising time needs to follow tCLCH spec.

4. Input data is latched on the rising edge of Serial Clock(SCLK) and data is shifted out on the falling edge of

SCLK. The difference of Serial mode 0 and mode 3 is shown in Figure 1.

5. For the following instructions:RDID, RDSR, RDSCUR, READ, FAST_READ, RDSFDP, DREAD, RES, and

REMS the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted

out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP, DP,

ENSA, EXSO,and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will

be rejected and not executed.

6. While a Write Status Register, Program, or Erase operation is in progress, access to the memory array is ne-

glected and will not affect the current operation of Write Status Register, Program, Erase.

Figure 1. Serial Modes Supported

CPOL CPHA

(Serial mode 0) 0

0

SCLK

(Serial mode 3) 1

1

SCLK

SI

SO

shift in

MSB

shift out

MSB

Note:

CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not

transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is

supported.

P/N: PM1944

REV. 1.1, DEC. 10, 2013

10

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