BD82HM55QMNT データシートの表示（PDF） - Intel
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BD82HM55QMNT Datasheet PDF : 934 Pages
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5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 121
5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) ..................................... 121
5.2.1 Interrupt Generation ............................................................................. 122
5.2.2 Power Management............................................................................... 122
5.2.2.1 S3/S4/S5 Support ................................................................... 122
5.2.2.2 Resuming from Suspended State ............................................... 123
5.2.2.3 Device Initiated PM_PME Message ............................................. 123
5.2.2.4 SMI/SCI Generation................................................................. 123
5.2.3 SERR# Generation ................................................................................ 124
5.2.4 Hot-Plug .............................................................................................. 124
5.2.4.1 Presence Detection .................................................................. 124
5.2.4.2 Message Generation ................................................................ 125
5.2.4.3 Attention Button Detection ....................................................... 125
5.2.4.4 SMI/SCI Generation................................................................. 126
5.3 Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 126
5.3.1 GbE PCI Express* Bus Interface.............................................................. 128
5.3.1.1 Transaction Layer.................................................................... 128
5.3.1.2 Data Alignment ....................................................................... 128
5.3.1.3 Configuration Request Retry Status ........................................... 128
5.3.2 Error Events and Error Reporting ............................................................ 129
5.3.2.1 Data Parity Error ..................................................................... 129
5.3.2.2 Completion with Unsuccessful Completion Status ......................... 129
5.3.3 Ethernet Interface ................................................................................ 129
5.3.3.1 Intel® 5 Series Chipset and Intel® 3400 Series Chipset
82577/82578 PHY Interface...................................................... 129
5.3.4 PCI Power Management ......................................................................... 130
5.3.4.1 Wake Up ................................................................................ 130
5.3.5 Configurable LEDs................................................................................. 131
5.3.6 Function Level Reset Support (FLR) ......................................................... 132
5.3.6.1 FLR Steps............................................................................... 132
5.4 LPC Bridge (with System and Management Functions) (D31:F0)............................. 133
5.4.1 LPC Interface ....................................................................................... 133
5.4.1.1 LPC Cycle Types ...................................................................... 134
5.4.1.2 Start Field Definition ................................................................ 134
5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR)..................................... 135
5.4.1.4 Size....................................................................................... 135
5.4.1.5 SYNC..................................................................................... 136
5.4.1.6 SYNC Time-Out ....................................................................... 136
5.4.1.7 SYNC Error Indication .............................................................. 136
5.4.1.8 LFRAME# Usage...................................................................... 136
5.4.1.9 I/O Cycles .............................................................................. 137
5.4.1.10 Bus Master Cycles ................................................................... 137
5.4.1.11 LPC Power Management ........................................................... 137
5.4.1.12 Configuration and PCH Implications ........................................... 137
5.5 DMA Operation (D31:F0) .................................................................................. 138
5.5.1 Channel Priority.................................................................................... 138
5.5.1.1 Fixed Priority .......................................................................... 138
5.5.1.2 Rotating Priority ...................................................................... 139
5.5.2 Address Compatibility Mode ................................................................... 139
5.5.3 Summary of DMA Transfer Sizes ............................................................. 139
5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words 139
5.5.4 Autoinitialize ........................................................................................ 140
5.5.5 Software Commands ............................................................................. 140
5.6 LPC DMA ........................................................................................................ 141
5.6.1 Asserting DMA Requests ........................................................................ 141
5.6.2 Abandoning DMA Requests..................................................................... 142
5.6.3 General Flow of DMA Transfers ............................................................... 142
5.6.4 Terminal Count..................................................................................... 142
5.6.5 Verify Mode ......................................................................................... 143
5.6.6 DMA Request De-assertion ..................................................................... 143
5.6.7 SYNC Field / LDRQ# Rules ..................................................................... 144
5.7 8254 Timers (D31:F0) ...................................................................................... 144
5.7.1 Timer Programming .............................................................................. 145
5.7.2 Reading from the Interval Timer ............................................................. 146
5.7.2.1 Simple Read ........................................................................... 146
5.7.2.2 Counter Latch Command .......................................................... 146
5.7.2.3 Read Back Command ............................................................... 146
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