MT46V16M16FG データシートの表示（PDF） - Micron Technology
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MT46V16M16FG Datasheet PDF : 80 Pages
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DOUBLE DATA RATE
(DDR) SDRAM
Features
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture (x16 has
two – one per byte)
• Internal, pipelined double data rate (DDR) architecture;
two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two – one
per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto Refresh and Self Refresh Modes
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option supported
• tRAS lockout supported (tRAP = tRCD)
OPTIONS
• Configuration
64 Meg x 4 (16 Meg x 4 x 4 banks)
32 Meg x 8 (8 Meg x 8 x 4 banks)
16 Meg x 16 (4 Meg x 16 x 4 banks)
• Plastic Package – OCPL
66-pin TSOP
66-pin TSOP (lead-free)1
• Plastic Package
60-Ball FBGA (16mm x 9mm)
60-Ball FBGA (16mm x 9mm)(lead-free)1
60-Ball FBGA (14mm x 8mm)
60-Ball FBGA (14mm x 8mm) (lead-free)1
• Timing – Cycle Time
6ns @ CL = 2.5 (DDR333)2 (FBGA only)
6ns @ CL = 2.5 (DDR333)2 (TSOP only)
7.5ns @ CL = 2 (DDR266)3
7.5ns @ CL = 2 (DDR266A)4
7.5ns @ CL = 2.5 (DDR266B)5, 6
• Self Refresh
Standard
Low-Power Self Refresh
• High-Speed Process Enhancement
Standard
High Speed
• Temperature Rating
Standard (0°C to +70°C)
Industrial Temperature (-40°C to +85°C)
MARKING
64M4
32M8
16M16
TG
P
FJ
BJ
FG
BG
-6
-6R/-6T
-75E
-75Z
-75
None
L
None
H
None
IT
256Mb: x4, x8, x16
DDR SDRAM
MT46V64M4 – 16 MEG x 4 x 4 BANKS
MT46V32M8 – 8 MEG x 8 x 4 BANKS
MT46V16M16 – 4 MEG x 16 x 4 BANKS
For the latest data sheet revisions, please refer to the
Micronâ Web site: www.micron.com/datasheets
Figure 1: Pin Assignment (Top View)
66-Pin TSOP
x4
x8
x16
VDD
VDD
VDD
1
NC DQ0 DQ0
2
VDDQ VDDQ VDDQ
3
NC
NC DQ1
4
DQ0 DQ1 DQ2
5
VSSQ VSSQ VssQ
6
NC
NC DQ3
7
NC DQ2 DQ4
8
VDDQ VDDQ VDDQ
9
NC
NC DQ5
10
DQ1 DQ3 DQ6
11
VSSQ VSSQ VssQ
12
NC
NC DQ7
13
NC
NC
NC
14
VDDQ VDDQ VDDQ
15
NC
NC LDQS
16
NC
NC NC
17
VDD
VDD
VDD
18
DNU DNU DNU
19
NC
NC LDM
20
WE# WE# WE#
21
CAS# CAS# CAS#
22
RAS# RAS# RAS#
23
CS# CS# CS#
24
NC
NC
NC
25
BA0 BA0 BA0
26
BA1 BA1 BA1
27
A10/AP A10/AP A10/AP
28
A0
A0 A0
29
A1
A1 A1
30
A2
A2 A2
31
A3
A3 A3
32
VDD
VDD
VDD
33
x16
x8
x4
66
VSS
VSS
VSS
65
DQ15 DQ7 NC
64
VSSQ VSSQ VSSQ
63
DQ14 NC
NC
62
DQ13 DQ6 DQ3
61
VDDQ VDDQ VDDQ
60
DQ12 NC
NC
59
DQ11 DQ5 NC
58
VSSQ VSSQ VSSQ
57
DQ10 NC
NC
56
DQ9 DQ4 DQ2
55
VDDQ VDDQ VDDQ
54
DQ8 NC
NC
53
NC
NC
NC
52
VSSQ VSSQ VSSQ
51
UDQS DQS DQS
50
DNU DNU DNU
49
VREF
VREF
VREF
48
VSS
VSS
VSS
47
UDM DM DM
46
CK# CK# CK#
45
CK
CK
CK
44
CKE CKE CKE
43
NC
NC
NC
42
A12 A12 A12
41
A11 A11 A11
40
A9
A9
A9
39
A8
A8
A8
38
A7
A7
A7
37
A6
A6
A6
36
A5
A5
A5
35
A4
A4
A4
34
VSS
VSS
VSS
64 MEG x 4
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
16 Meg x 4 x 4
banks
8K
8K (A0–A12)
4 (BA0,BA1)
2K (A0–A9,A11)
32 MEG x 8
8 Meg x 8 x 4
banks
8K
8K (A0–A12)
4 (BA0,BA1)
1K (A0–A9)
16 MEG x 16
4 Meg x 16 x 4
banks
8K
8K (A0–A12)
4 (BA0,BA1)
512 (A0–A8)
Table 1: Key Timing Parameters
SPEED
GRADE
CLOCK RATE7
DATA-OUT ACCESS DQS–DQ
CL=2 CL=2.5 WINDOW8 WINDOW SKEW
-6
-6R/-6T
-75E/-75Z
-75
133 MHz
133 MHz
133 MHz
100 MHz
167 MHz
167 MHz
133 MHz
133 MHz
2.1ns
2.0ns
2.5ns
2.5ns
±0.7ns
±0.7ns
±0.75ns
±0.75ns
+0.40ns
+0.45ns
+0.5ns
+0.5ns
NOTE:
1. Contact Micron for availability of lead-free products.
2. Supports PC2700 modules with 2.5-3-3 timing.
3. Supports PC2100 modules with 2-2-2 timing.
4. Supports PC2100 modules with 2-3-3 timing.
5. Supports PC2100 modules with 2.5-3-3 timing.
6. Supports PC1600 modules with 2-2-2 timing.
7. CL=CAS(READ) latency.
8. Minimum clock rate @ CL = 2 (-75E, -75Z), @ CL = 2.5
(-6T, -6R, -75)
09005aef8076894f
256MBDDRx4x8x16_1.fm - Rev. F 6/03 EN
1
©2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
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