TMP88CS38/CM38A/CP38A
DV1CK
High-frequency
clock
Timer/
counters
fm
Machine cycle counters
Machine cycles
States
Prescaler S
Divider
Divider
fc
A
fc/28
012
Y 123456
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
B
Reset circuit
standby
controller
Watchdog
timer
fc
MK8 MHz FC8OUT
D1
D0
SLICER
Time base
timer
SG
JITTA
Figure 1.4.3 Configuration of Timing Generator
CGCR
(00030H)
“0”
“0” DV1CK “0”
“0”
“0”
“0”
“0”
DV1CK
Selection of input clock to 0: fc/4
the 1st stage of the divider. 1: fc/8
Note 1: fc: High-frequency clock [Hz], *: Don’t care
Note 2: The all bits except DV1CK are cleared to “0”.
Figure 1.4.4 Divider Control Register
(Initial value: 0000 0000)
R/W
FC8CR
(00FEEH)
D1
D0
1
0
0
0
D1
FC8OUT
1/2 fc
1/1 fc
D0 Read/Write (Initial value: 0000 0010)
Figure 1.4.5 FC8 Control Register
88CS38-10
2007-09-12