ADRF6655-EVALZ データシートの表示（PDF） - Analog Devices

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ADRF6655-EVALZ

Broadband Up/Downconverting Mixer with Integrated Fractional-N PLL and VCO

Analog Devices 

ADRF6655

Pin No.

5

Mnemonic

RSET

6

REFIN

8

MUXOUT

9

10

12

13

14

16, 32, 33

17, 34

18,19

22

25, 26

27

29

37, 38

DECL2

VCC2

DATA

CLK

LE

NC

VCCLO

OUTN, OUTP

VCCV2I

INN, INP

VCCMIX

IP3SET

LON, LOP

39

VTUNE

40

DECL3

EPAD (EP)

Description

Charge Pump Current. The nominal charge pump current can be set to either 250 μA, 500 μA, 750 μA,

or 1 mA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (internal reference current).

In this mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents

(INOMINAL) can be externally tweaked according to

RSET

[Ω ] =

⎡ 217 .4 × I CP ,BASE

⎢⎣

250

⎤

⎥⎦

−

37 .8

where ICP, BASE is the base charge pump current in μA.

For further details on the charge pump current,see the Register 4—Charge Pump, PFD, and Reference

Path Control section.

Reference Input. Nominal input level is 1 V p-p. Input range is 10 MHz to 160 MHz. This pin must be

ac-coupled.

Multiplexer Output. This output allows either a digital lock detect, a voltage proportional to temperature,

or a buffered, frequency-scaled reference signal to be accessed externally. The output is selected by

programming the appropriate bits in Register 4.

Decoupling Node for 2.5 V LDO. Pin should be decoupled with 100 pF, 0.1 μF, and 10 μF capacitors

located close to the pin.

Power Supply for Internal 2.5 V LDO. The power supply voltage range is 4.75 V to 5.25 V. Supply pin

should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin.

Serial Data Input. The serial data input is loaded MSB first with the three LSBs being the control bits.

Serial Clock Input. This serial clock input is used to clock in the serial data to the registers. The data

is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz.

Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one

of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word.

No Connection.

Power Supply for LO Path. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be

decoupled with 100 pF and 0.1 μF capacitors located close to the pin.

Mixer IF Outputs. These pins should be pulled to VCC with RF chokes.

Power Supply for Voltage to Current Input Stage. The power supply voltage range is 4.75 V to 5.25 V.

Supply pin should be decoupled with 100 pF and 0.1 μF capacitors located close to the pin.

Mixer RF Inputs. Differential RF Inputs. Internally matched to 50 Ω. This pin must be ac-coupled.

Power Supply for Mixer. The power supply voltage range is 4.75 V to 5.25 V. Supply pin should be

decoupled with 100 pF and 0.1 μF capacitors located close to the pin.

Connect Resistor to VCC to Adjust IP3.

Local Oscillator Input/Output. The internally generated 1 × fLO is available on these pins. When internal

LO generation is disabled, an external 2 × fLO or 3 × fLO (depending on divider selection) can be applied

to these pins. This pin must be ac-coupled.

VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage

range on this pin is 1 V to 2.8 V.

Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin

and ground.

The exposed paddle should be soldered to a low impedance ground plane.

Rev. 0 | Page 8 of 44

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