NT1GD64S8HB0FM データシートの表示（PDF） - Nanya Technology
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NT1GD64S8HB0FM
Nanya Technology
NT1GD64S8HB0FM Datasheet PDF : 14 Pages
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NT1GD64S8HA0FM / NT1GD64S8HB0FM
1GB : 128M x 64
PC2700 / PC2100 Unbuffered DDR SO-DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
TA = 0 °C ~ 70 °C; VDDQ = VDD = 2.5V ± 0.2V (Part 1 of 2)
Symbol
tAC
tDQSCK
tCH
tCL
tCK
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock cycle time
CL=2.5
CL=2
6K
Min. Max.
-0.7
+0.7
-0.7
+0.7
0.45
0.55
0.45
0.55
6
12
7.5
12
75B
Unit
Min. Max.
-0.75 +0.75 ns
-0.75 +0.75 ns
0.45
0.55
tCK
0.45
0.55
tCK
7.5
12
ns
10
12
ns
tDH
DQ and DM input hold time
0.45
0.5
ns
Notes
1-4
1-4
1-4
1-4
1-4
1-4
1-4,
15, 16
tDS
DQ and DM input setup time
tDIPW
DQ and DM input pulse width (each input)
0.45
1.75
0.5
1.75
1-4,
ns
15, 16
ns
1-4
tHZ
Data-out high-impedance time from CK/CK
-0.7
+0.7 -0.75 +0.75 ns 1-4, 5
tLZ
tDQSQ
tHP
tQH
tQHS
tDQSS
tDQSL,
tDQSH
tDSS
tDSH
tMRD
tWPRES
tWPST
tWPRE
tIH
tIS
tIH
Data-out low-impedance time from CK/CK
DQS-DQ skew (DQS & associated DQ signals)
Minimum half clk period for any given cycle; defined
by clk high (tCH) or clk low (tCL) time
Data output hold time from DQS
Data hold Skew Factor
Write command to 1st DQS latching transition
DQS input low (high) pulse width
(write cycle)
DQS falling edge to CK setup time
(write cycle)
DQS falling edge hold time from CK
(write cycle)
Mode register set command cycle time
Write preamble setup time
Write postamble
Write preamble
Address and control input hold time
(fast slew rate)
Address and control input setup time
(fast slew rate)
Address and control input hold time
(slow slew rate)
-0.7
tCH or
tCL
tHP -
tQHS
0.75
0.35
0.2
0.2
2
0
0.40
0.25
0.75
0.75
0.8
+0.7
0.45
0.55
1.25
0.60
-0.75 +0.75 ns 1-4, 5
0.5
ns
1-4
tCH or
tCL
tCK
1-4
tHP -
tQHS
tCK
1-4
0.75 ns
1-4
0.75
1.25
tCK
1-4
0.35
tCK
1-4
0.2
tCK
1-4
0.2
tCK
1-4
2
tCK
1-4
0
ns 1-4, 7
0.40
0.25
0.9
0.9
1.0
0.60
tCK 1-4, 6
tCK
1-4
2-4, 9,
ns
11, 12
2-4, 9,
ns
11, 12
2-4,
ns 10, 11,
12, 14
REV 1.2
12/19/2003
Preliminary
10
© NANYA TECHNOLOGY CORPORATION
NANYA reserves the right to change products and specifications without notice.
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