NT1GD64S8HB0FM データシートの表示（PDF） - Nanya Technology

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NT1GD64S8HB0FM

1GB, 512MB and 256MB 200 pin Unbuffered DDR SO-DIMM Based on DDR333 512Mb bit B Die device

Nanya Technology 

NT1GD64S8HA0FM / NT1GD64S8HB0FM

1GB : 128M x 64

PC2700 / PC2100 Unbuffered DDR SO-DIMM

Operating, Standby, and Refresh Currents

TA = 0 °C ~ 70 °C; VDDQ = VDD = 2.5V ± 0.2V

Symbol

Parameter/Condition

PC2700

(6K)

IDD0

Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and

DQS inputs changing twice per clock cycle; address and control inputs changing once

per clock cycle

1466

IDD1

IDD2P

IDD2N

IDD3P

IDD3N

Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK =

tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle

Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ VIL

(MAX); tCK = tCK (MIN)

Idle Standby Current: CS ≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK = tCK (MIN); address

and control inputs changing once per clock cycle

Active Power-Down Standby Current: one bank active; power-down mode; CKE ≤ VIL

(MAX); tCK = tCK (MIN)

Active Standby Current: one bank; active/precharge; CS ≥ VIH (MIN); CKE ≥ VIH (MIN); tRC =

tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address

and control inputs changing once per clock cycle

1625

165

533

214

765

Operating Current: one bank; Burst = 2; reads; continuous burst; address and control

IDD4R inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock

cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA

Operating Current: one bank; Burst = 2; writes; continuous burst; address and control

IDD4W inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock

cycle; CL=2.5; tCK = tCK (MIN)

IDD5 Auto-Refresh Current: tRC = tRFC (MIN)

1840

1720

3429

IDD6 Self-Refresh Current: CKE ≤ 0.2V

64

Operating Current: four bank; four bank interleaving with BL = 4, address and control

IDD7 inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT =

0mA.

1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns.

3. Current at 7.8 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 µs.

3774

PC2100

(75B)

1289

1568

165

520

220

775

1964

1584

2894

64

3918

Unit Notes

mA 1,2

mA 1,2

mA 1,2

mA 1,2

mA 1,2

mA 1,2

mA 1,2

mA 1,2

mA 1,2,3

mA 1,2

mA 1,2

REV 1.2

12/19/2003

Preliminary

9

© NANYA TECHNOLOGY CORPORATION

NANYA reserves the right to change products and specifications without notice.

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