74LVC1G74DP-Q100 データシートの表示（PDF） - NXP Semiconductors.
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74LVC1G74DP-Q100
NXP Semiconductors.
74LVC1G74DP-Q100 Datasheet PDF : 18 Pages
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NXP Semiconductors
74LVC1G74-Q100
Single D-type flip-flop with set and reset; positive edge trigger
7. Functional description
Table 4.
Input
SD
L
H
L
Function table for asynchronous operation[1]
RD
CP
D
H
X
X
L
X
X
L
X
X
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
Output
Q
Q
H
L
L
H
H
H
Table 5. Function table for synchronous operation[1]
Input
SD
RD
CP
D
H
H
L
H
H
H
[1] H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH CP transition.
8. Limiting values
Output
Qn+1
L
H
Qn+1
H
L
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
IIK
input clamping current
VI < 0 V
VI
input voltage
IOK
output clamping current
VO > VCC or VO < 0 V
VO
output voltage
Active mode
Power-down mode
0.5
50
[1] 0.5
-
[1] 0.5
[1][2] 0.5
+6.5
V
-
mA
+6.5
V
50
mA
VCC + 0.5 V
+6.5
V
IO
ICC
IGND
Ptot
Tstg
output current
supply current
ground current
total power dissipation
storage temperature
VO = 0 V to VCC
Tamb = 40 C to +125 C
-
50
mA
-
100
mA
100
-
mA
[3] -
300
mW
65
+150
C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 packages: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.
For XSON8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
74LVC1G74_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
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