AT24C08D データシートの表示（PDF） - Atmel Corporation

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AT24C08D

I2C-Compatible (2-wire) Serial EEPROM 8-Kbit (1,024 x 8)

Atmel Corporation 

3. Device Operation and Communication

The AT24C08D operates as a slave device and utilizes a simple I2C-compatible 2-wire digital serial interface to

communicate with a host controller, commonly referred to as the bus Master. The Master initiates and controls all

Read and Write operations to the slave devices on the serial bus, and both the Master and the slave devices can

transmit and receive data on the bus.

The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA). The SCL pin is

used to receive the clock signal from the Master, while the bidirectional SDA pin is used to receive command and

data information from the Master as well as to send data back to the Master. Data is always latched into the

AT24C08D on the rising edge of SCL and always output from the device on the falling edge of SCL. Both the SCL

and SDA pin incorporate integrated spike suppression filters and Schmitt Triggers to minimize the effects of input

spikes and bus noise.

All command and data information is transferred with the Most Significant Bit (MSB) first. During bus

communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data have been

transferred, the receiving device must respond with either an acknowledge (ACK) or a no-acknowledge (NACK)

response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by the Master. Therefore, nine clock

cycles are required for every one byte of data transferred. There are no unused clock cycles during any Read or

Write operation, so there must not be any interruptions or breaks in the data stream during each data byte transfer

and ACK or NACK clock cycle.

During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain stable

while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will

occur. Start and Stop conditions are used to initiate and end all serial bus communication between the Master and

the slave devices. The number of data bytes transferred between a Start and a Stop condition is not limited and is

determined by the Master. In order for the serial bus to be idle, both the SCL and SDA pins must be in the

logic-high state at the same time.

3.1 Clock and Data Transition Requirements

The SDA pin is an open drain terminal and therefore must be pulled high with an external pull-up resistor. Data on

the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a

Start or Stop condition as defined below.

3.2 Start and Stop Conditions

3.2.1

Start Condition

A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at a stable

Logic 1 state and will bring the device out of standby mode. The Master uses a Start condition to initiate any data

transfer sequence; therefore, every command must begin with a Start condition. The device will continuously

monitor the SDA and SCL pins for a Start condition but will not respond unless one is detected. Please refer to

Figure 3-1 for more details.

3.2.2 Stop Condition

A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the

Logic 1 state. The Master can use the Stop condition to end a data transfer sequence with the AT24C08D which

will subsequently return to standby mode. The Master can also utilize a repeated Start condition instead of a Stop

condition to end the current data transfer if the Master will perform another operation. Please refer to Figure 3-1 for

more details.

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AT24C08D [DATASHEET]

Atmel-8880B-SEEPROM-AT24C08D-Datasheet_042014

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