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CXA1998BQ データシートの表示(PDF) - Sony Semiconductor

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CXA1998BQ
Sony
Sony Semiconductor Sony
CXA1998BQ Datasheet PDF : 28 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
CXA1998BQ
Make sure that VDD is 4.0V or more and XRESET is 1.5V or less, and 1µs or more when resetting by
applying CR time constant to XRESET (Pin 27) and turning power ON.
4.0V or more
VDD
(Pin 23)
1.5V or less
XRESET
(Pin 27)
1µs or more
A
XRESET (Pin 27) input level detection is done by comparison with VDD/2.
The level should be VDD/2 > XRESET during the interval A.
For resetting with CPU when power is turned ON
4.0V or more
VDD
(Pin 23)
XRESET
(Pin 27)
0V
1µs or more
5.0V
Examples of AGC control during timer recording
(1) Resets when power is turned ON (AGC function operates).
(2) AGC is turned OFF after AGC inputs (Pins 5 and 32) rise.
(External capacitor charge of AGC TC is discharged.)
(3) AGC is turned ON and timer recording begins.
– 19 –

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