M61529FP データシートの表示（PDF） - Hitachi -> Renesas Electronics

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M61529FP

Audio Signal Processor with Surround

Hitachi -> Renesas Electronics 

M61529FP

Rerationship Between Data and Clock and Latch

DATA

D0

D1

D2

D3

D4

D5

D6

D7

Latch signal=“H”

D15

CLOCK

DATA signal is read at the rising edge of CLOCK

Latch signal is read at the falling edge of CLOCK

Data Timing (Recommended conditions)

(D0 ~ D15)

tcr

(D15)LATCH pulse

DATA

tSLD tHLD tSHD tHHD

75%

CLOCK

25%

tr

tWHC

tf

tWLC

Digital Block Timing Regulation

Symbol

tcr

t

WHC

t

WLC

tr

tf

t

SHD

t

SLD

t

HHD

t

HLD

Parameter

CLOCK cycle time

CLOCK pulse width ("H" level)

CLOCK pulse width ("L" level)

CLOCK rise time

CLOCK fall time

DATA setup time ("H" level) CLOCK rise

DATA setup time ("L" level) CLOCK rise

DATA hold time ("H" level)

DATA hold time ("L" level)

tSLD

tHLD

Limits

Min

typ

Max

Unit

4

—

—

1.6

—

—

1.6

—

—

—

—

0.4

—

—

0.4

µs

0.8

—

—

0.8

—

—

0.8

—

—

0.8

—

—

Rev.1.00, Sep.04.2003, page 6 of 23

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