ACD81024 データシートの表示（PDF） - Unspecified

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ACD81024

24 Ports Single Chip 10Base-T Ethernet Switch Designed For Desktop Environment

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3. OPERATIONAL DESCRIPTION

ACD81024 Ethernet switch is composed by six types

of logic modules: the Physical Layer (PHY) circuitry,

the Media Access Control (MAC) logic, the Lookup

Engine, the Switching Fabric, the Fabric Control logic,

and the LED Control logic. On the receiving side, the

PHY circuitry converts the analog voltages coming

from the unshielded twist pair cable into digital signals

suitable for digital processing, and decodes the

received data in Manchester code into NRZ code. On

the transmitting side, the PHY circuitry translates the

data to be transmitted from NRZ code into Manches-

ter code, and then converts the data into analog

signals suitable to drive unshielded twist pair cable.

The MAC logic of a port controls the transmit, re-

ceive, defer, and congestion control process of the

port. The Lookup Engine provides mapping between

a destination MAC address and a destination port

number. The Switching Fabric is used to establish

communication channels between the source ports

and the associated destination ports. The Fabric

Control logic controls the construction/destruction of

the communication channels. The LED Control logic

displays various kinds of port status of the switch.

ACD81024 is designed as a desktop class Ethernet

switch. Only one DTE with one MAC address can be

connected to each port of ACD81024, except the

expansion port.

When an Ethernet frame comes from a data termina-

tion device (DTE) through a 10Base-T network media

(UTP) into a source port of ACD81024 switch, the

signal, encoded in Manchester code, is amplified by

the twist pair receiver circuitry of the source port and

converted into a NRZ data signal and a recovered

clock signal by the decoder circuitry of the source

port. The NRZ data signal is then processed by the

MAC logic of the source port. The information of the

destination address (DA) and the source address

(SA) embedded inside the frame are retrieved. The

SA is used to update the port’s MAC address stored

in the Lookup Engine. The DA is used to identify the

destination port. Once the destination port is identi-

fied, the Fabric Control logic checks the status of the

destination port(s) to see if the destination port(s) is

ready to receive the data. If so, the Fabric Control

logic establishes the communication channel(s)

between the source port and the destination port(s)

inside the Switching Fabric. The MAC logic of the

source port forwards the received data to the estab-

lished the communication channel in the Switching

Fabric. The MAC logic of the destination port(s)

receives the data from the communication channel in

the Switching Fabric and forwards the data to the

destination port’s Physical Layer circuitry. The

Manchester encoder circuitry translates the data into

Manchester code and sends to the port’s twist pair

transmitter circuitry. The transmitter circuitry converts

the data into analog levels suitable to drive the

10Base-T network media between the switch and the

destination DTE. If collision is detected during a

transmission process, the destination port MAC logic

will end the frame with a Jam pattern. The source port

MAC logic will stop forwarding the frame data and

send a Jam pattern back to the source DTE.

If the destination port headed by an incoming frame is

not ready to receive the data, the MAC logic of the

source port will send a Jam pattern to the source

DTE. According to IEEE 802.3 CSMA/CD scheme,

the source DTE will retransmit the frame after a pre-

determined back-off time period. In order to prevent

the source DTE from sending the frame before the

destination port is ready, ACD81024 continuously

sends a Back Pressure signal to the source DTE to

cause its Carrier Sense signal to be asserted. The

transmit-defer-on-carrier-sense nature of CSMA/CD

scheme will prevent the source DTE from sending the

frame as long as the Carrier Sense signal is asserted.

The Back Pressure signal is released when the

destination port(s) is ready to receive new frame.

Different from a typical Ethernet frame switch,

ACD81024 does not store the received data into data

buffer. Instead, it sends the data directly to the

destination port in cut-through mode. In collision

domain isolation perspective, ACD81024 behaves

like a shared-media repeater. Once collision is

detected on the destination port, a Jam pattern is sent

to the source DTE to force collision detection. Differ-

ent from a shared-media repeater, collision is caused

by concurrent transmission activities of the source

DTE and the destination DTE(s), not any DTE

connected with the switch. In other words, the colli-

sion domain is minimized to the source port and the

corresponding destination port(s).

4. FUNCTIONAL DESCRIPTION

4.1 PHY Module

ACD81024 provides built-in twist pair transmitter/

receiver (transceiver) circuitry for each port. Besides,

each PHY module also contains the logic for polarity

detection and automatic correction, Manchester code

encoding and decoding, clock data recovery, and link

pulse detection and generation. All circuits are

implemented to be 100% compatible with IEEE 802.3

requirement.

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

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