ACD81024 データシートの表示（PDF） - Unspecified

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ACD81024

24 Ports Single Chip 10Base-T Ethernet Switch Designed For Desktop Environment

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Twist Pair Transmitter

The twist pair transmitter converts the digital output

signal into analog voltages necessary to drive

unshielded twist pair cable. Different from most other

implementations, the transmitter circuitry inside

ACD81024 uses two output pins (as opposed to four)

and internally generates emphasis/de-emphasis

voltage levels required to compensate for the twist

pair cable. The waveform of each kind of output

signal is described in the chapter of “Signal Wave-

forms.”

and at same time, generates a recovered clock

signal. The recovered clock signal is used to latch

the NRZ data into a synchronization FIFO. The NRZ

data is read out of the FIFO using the system clock.

Manchester Encoding

On the transmit side, the NRZ data coming from the

MAC logic is converted into Manchester code by the

Manchester encoder circuitry. The data is then

passed to the 10Base-T transceiver circuitry for

transmission onto the network media.

Twist Pair Receiver

Link Pulse Detection

The Twist Pair Receiver converts the analog voltages

coming from the unshielded twist pair cable into TTL

level signals suitable for digital processing.

Each Twist Pair Receiver of ACD81024 is equipped

with a smart squelch circuitry to ensure that noise on

the receive pair will not be treated as valid frame data

signals. The squelch circuitry employs a combination

of both amplitude and timing measurement to deter-

mine the validity of received data signal. Only valid

data will be passed to the Manchester Decoder

circuitry. Validity of data is determined by following

three conditions:

1 The signal crosses the positive threshold level

of +365 mV or negative threshold level of -365

mV.

2 The signal has to cross the other threshold

level within 150 ns.

3 The signal has to cross the original threshold

within 150 ns.

The waveform of signal received by the smart

squelch circuitry is described in the chapter of “Signal

Waveforms.”

On the receive side, each PHY module has a link

pulse detection circuitry. If no link pulse is received for

50 ms, a link test fail signal will be sent to the port’s

MAC logic circuitry to cause it enter the Link Fail

state. In Link Fail state, the Link LED signal of the

port is deserted. However, transmission from the port

is not disabled. Any traffic heading for this port will still

be forwarded to it. When the PHY circuitry receives a

valid link pulse, or receives a continuous bit stream, it

signals the MAC logic for valid link status and causes

MAC logic enter the Link Pass state immediately. The

waveform of a link pulse to be detected by the link

pulse detector is shown in the chapter of “Signal

Waveforms.” The link pulse detection function can be

disabled by pulling low the LNKE signal.

Link Integrity Pulse Generation

On the transmit side, each PHY module has a link

pulse generation circuitry. When there is no transmis-

sion activity on the transmission pair, the link pulse

generation circuitry generates one link pulse for every

16 ms. The width of the link pulse is 100ns. The

waveform of the link pulse generated by ACD81024 is

shown in the chapter of “Signal Waveforms.”

Polarity Detection and Correction

Polarity Detection circuitry uses the incoming link

pulses to check for polarity reversal. If the polarity of

the signal is detected to be reversed, the Polarity

Correction logic automatically inverts the receiving

pair. Therefore, the MAC logic circuitry will always

receive the signal in correct polarity.

4.2 MAC Module

The MAC module controls the transmit, receive,

defer, and congestion control process of a port,

according to IEEE 802.3 standard.

Frame Format

Manchester Decoding

On the receive side, after passing through the polarity

detection and automatic correction circuitry, the

incoming signal is processed by the Manchester

decoder circuitry. The Manchester decoder converts

the Manchester code data signal into NRZ data signal

ACD81024 assumes the data frame coming into the

switch have the following format:

Where,

Preamble SFD DA SA Type/Len Data FCS

ACD Confidential. Do Not Reproduce. Use under Non-Disclosure agreement only.

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