LTC6803 データシートの表示（PDF） - Linear Technology

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LTC6803

Multicell Battery Stack Monitor

Linear Technology 

LTC6803-1/LTC6803-3

APPLICATIONS INFORMATION

the resistive loading on the cell group when the IC enters

standby mode (i.e., when WDTB goes low). An LT6004

micropower operational amplifier section is shown for

buffering the divider signal to preserve accuracy. This

circuit has the virtue that it can be converted about four

times more frequently than the entire battery array, thus

offering a higher sample rate option at the expense of

some precision/accuracy, reserving the high resolution

cell readings for calibration and balancing data.

PROVIDING HIGH SPEED ISOLATION OF THE SPI DATA

PORT

Isolation techniques that are capable of supporting the

1Mbps data rate of the LTC6803 require more power on

the isolated (battery) side than can be furnished by the

VREG output of the LTC6803. To keep battery drain minimal,

this means that a DC/DC function must be implemented

along with a suitable data isolation circuit, such as shown

in Figure 22. A quad (3 + 1) data isolator Si8441AB-C-IS

is used to provide non-galvanic SPI signal connections

between a host microprocessor and an LTC6803. An

inexpensive isolated DC/DC converter provides power-

ing of the isolator function completely from the host 5V

power supply. A quad three-state buffer is used to allow

SPI inputs at the LTC6803 to rise to logic high level when

the isolator circuitry powers down, assuring the lowest

power consumption in the standby condition. The pull-

ups to VREG are selected to match the internal loading on

VREG by ICs operating with a current mode SPI interface,

thus balancing the current in all cells during operation.

The additional pull-up on the SDO line (1k resistor and

Schottky diode) is to improve rise time, in lower data-rate

applications this may not be needed.

5V_HOST

SPI_CLOCK

SPI_CHIPSELECT

SPI_MASTEROUT

SPI_MASTERIN

GND_HOST

100Ω

100Ω

100Ω

100Ω

1µF

1µF

470pF

20.0k

10.0k

1 LTC1693-2 8

IN1 VCC1

2

7

GND1 OUT1

3

IN2

6

VCC2

4

5

GND2 OUT2

Si8441AB-C-IS

QUAD ISOLATOR

1 VDD1

VDD2 16

2 GND1 GND2 15

3 A1

B1 14

4 A2

B2 13

5 A3

B3 12

6 A4

B4 11

7 EN1

EN2 10

8 GND1 GND2 9

33nF

PE-68386

1• •6

3

4

CMDSH2-3

1k

13

12 11

1/4 74ABT126

1

2

3

4

1/4 74ABT126 5

6

1µF

1/4 74ABT126 10

89

1/4 74ABT126

BAT54S

74ABT126 SUPPLY SHARED WITH

ISOLATOR VDD2 and GND2

4.22k

4.22k

4.22k

4.22k

VREG

SCKI

CSB1

SCI

SDO

V–

680313 F22

Figure 22. Providing an Isolated High Speed Data Interface

680313f

34

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