74LVC240APW データシートの表示（PDF） - NXP Semiconductors.

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74LVC240APW

Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state

NXP Semiconductors. 

NXP Semiconductors

5. Pinning information

5.1 Pinning

74LVC240A

Octal buffer/line driver with 5 V tolerant inputs/outputs; inverting;

3-state

1OE 1

1A0 2

2Y0 3

1A1 4

2Y1 5

1A2 6

2Y2 7

1A3 8

2Y3 9

GND 10

20 VCC

19 2OE

18 1Y0

17 2A0

16 1Y1

240

15 2A1

14 1Y2

13 2A2

12 1Y3

11 2A3

001aad036

Fig 4. Pin configuration for SO20 and (T)SSOP20

terminal 1

index area

1A0 2

2Y0 3

1A1 4

2Y1 5

1A2 6

2Y2 7

1A3 8

2Y3 9

240

GND(1)

19 2OE

18 1Y0

17 2A0

16 1Y1

15 2A1

14 1Y2

13 2A2

12 1Y3

001aad037

Transparent top view

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 5. Pin configuration for DHVQFN20

5.2 Pin description

Table 2.

Symbol

1OE

2OE

1A[0:3]

2A[0:3]

1Y[0:3]

2Y[0:3]

GND

VCC

Pin description

Pin

1

19

2, 4, 6, 8

17, 15, 13, 11

18, 16, 14, 12

3, 5, 7, 9

10

20

Description

output enable input (active LOW)

output enable input (active LOW)

data input

data input

data output

data output

ground (0 V)

power supply

74LVC240A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 8 — 29 November 2011

© NXP B.V. 2011. All rights reserved.

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