MPC931 データシートの表示（PDF） - Motorola => Freescale
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MPC931 Datasheet PDF : 14 Pages
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‘0’
‘1’
‘0’
‘0’
16.66MHz
MPC930
Div_Sela
Div_Selb
Div_Selc
ExtFB_Sel
Input Ref
2
Qa
2
Qb
2
Qc
66.66MHz (Processor)
33.33MHz (PCI)
33.33MHz (PCI)
Figure 5. Dual Frequency Configuration
MPC930 MPC931
‘1’
‘1’
‘0’
‘0’
16.66MHz
MPC930
Div_Sela
Div_Selb
Div_Selc
ExtFB_Sel
Input Ref
2
Qa
2
Qb
2
Qc
33.33MHz
33.33MHz
33.33MHz
Figure 6. Single Frequency Configuration
‘1’
‘1’
‘1’
‘1’
33.33MHz
MPC931
Div_Sela
Div_Selb
Div_Selc
ExtFB_Sel
Ext_FB
Input Ref
2
Qa
2
Qb
2
Qc
1
50MHz
50MHz
33.33MHz
Figure 7. “Zero” Delay Fractional Multiplier
‘0’
‘1’
‘1’
‘1’
50MHz
MPC931
Div_Sela
Div_Selb
Div_Selc
ExtFB_Sel
Ext_FB
Input Ref
2
Qa
2
Qb
2
Qc
1
100MHz
50MHz
33.33MHz
Figure 8. “Zero” Delay Fractional Divider
‘0’
‘0’
‘1’
‘1’
33.33MHz
MPC931
Div_Sela
Div_Selb
Div_Selc
ExtFB_Sel
Ext_FB
Input Ref
2
Qa
2
Qb
2
Qc
1
100MHz
100MHz
33.33MHz
‘0’
‘0’
‘1’
‘1’
100MHz
MPC931
Div_Sela
Div_Selb
Div_Selc
ExtFB_Sel
Ext_FB
Input Ref
2
Qa
2
Qb
2
Qc
1
100MHz
100MHz
33.33MHz
Figure 9. “Zero” Delay Multiply by 3 (50% Duty Cycle)
Figure 10. “Zero” Delay Divide by 3 (50% Duty Cycle)
Using the MPC930/931 as a Zero Delay Buffer
The external feedback option of the MPC930/931 clock
driver allows for its use as a zero delay buffer. By using one of
the outputs as a feedback to the PLL the propagation delay
through the device is eliminated. The PLL works to align the
output edge with the input reference edge thus producing a
near zero delay. The Tpd of the device is specified in the
specification tables. For zero delay buffer applications, the
MPC931 is recommended over the MPC930. The MPC931
has been optimized and specified specifically for use as a
zero delay buffer.
When used as a zero delay buffer the MPC930/931 will
likely be in a nested clock tree application. For these
applications the MPC931 offers a LVPECL clock input as a
PLL reference. This allows the user to use LVPECL as the
primary clock distribution device to take advantage of its far
superior skew performance. The MPC931 then can lock onto
the LVPECL reference and translate with near zero delay to
low skew LVCMOS outputs. Clock trees implemented in this
fashion will show significantly tighter skews than trees
developed from CMOS fanout buffers.
To minimize part–to–part skew the external feedback
option again should be used. The PLL in the MPC931
decouples the delay of the device from the propagation delay
variations of the internal gates. From the specification table
one sees a Tpd variation of only ±150ps, thus for multiple
devices under identical configurations the part–to–part skew
will be around 850ps (300ps for Tpd variation plus 300ps
TIMING SOLUTIONS
7
BR1333 — Rev 6
MOTOROLA
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