ATF22V10BQL-25NM/883 データシートの表示（PDF） - Atmel Corporation

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ATF22V10BQL-25NM/883

High-performance Electrically Erasable Programmable Logic Device

Atmel Corporation 

10. Preload of Registered Outputs

The Atmel® ATF22V10B registers are provided with circuitry to allow loading of each register with either a high or a

low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A

JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC

file preload sequence will be done automatically by most of the approved programmers after the programming.

Figure 10-1.

Table 10-1.

Parameter

tPR

VRST

Description

Power-up

Reset Time

Power-up

Reset

Voltage

Typ Max Units

600 1,000

ns

3.8

4.5

V

11. Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF22V10B fuse patterns. Once programmed,

fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.

The security fuse should be programmed last, as its effect is immediate.

12. Electronic Signature Word

There are 64-bits of programmable memory that are always available to the user, even if the device is secured.

These bits can be used for user-specific data.

13. Programming/Erasing

Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming

Hardware and Software Support for information on software/programming.

6 Atmel ATF22V10B

0250M–PLD–7/10

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