QL6250-E-7PT280M データシートの表示（PDF） - QuickLogic Corporation

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QL6250-E-7PT280M

FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

4/( (FOLSVH( 'DWD 6KHHW 5HY $

7DEOH  (FOLSVH( 2XWSXW 5HJLVWHU &HOO

6\PERO

3DUDPHWHU

2XWSXW 5HJLVWHU &HOO 2QO\

0LQ

tOUTLH Output Delay low to high (90% of H)

-

tOUTHL Output Delay high to low (10% of L)

-

tPZH Output Delay tri-state to high (90% of H)

-

tPZL

Output Delay tri-state to low (10% of L)

-

tPHZ

Output Delay high to tri-State

-

tPLZ

Output Delay low to tri-State

-

tCOP Clock-to-out delay (does not include clock tree delays)

-

9DOXH

0D[

0.40 ns

0.55 ns

2.94 ns

2.34 ns

3.07 ns

2.53 ns

3.15 ns (fast slew)

10.2 ns (slow slew)

H

L

H

Z

L

H

Z

L

Rising Edge

Falling Edge

H

tOUTHL

L

tOUTLH

H

tPZH

Z

L

H

tPZL

tPHZ

Z

L

tPLZ

)LJXUH  (FOLSVH( 2XWSXW 5HJLVWHU &HOO 7LPLQJ

7DEOH  2XWSXW 6OHZ 5DWHV # 9&&,2  9

)DVW 6OHZ

2.8 V/ns

2.86 V/ns

6ORZ 6OHZ

1.0 V/ns

1.0 V/ns

Rising Edge

Falling Edge

7DEOH  2XWSXW 6OHZ 5DWHV # 9&&,2  9

)DVW 6OHZ

1.7 V/ns

1.9 V/ns

6ORZ 6OHZ

0.6 V/ns

0.6 V/ns

Preliminary ‹  4XLFN/RJLF &RUSRUDWLRQ

ZZZTXLFNORJLFFRP ‡‡‡‡‡‡



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