QL6250-E-6PS484I データシートの表示（PDF） - QuickLogic Corporation

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QL6250-E-6PS484I

FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

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tRESET

Reset Delay: time between when the flip-flop is ”reset” (low) and when the output

is consequently “reset” (low)

-

0.09 ns

tSW

Set Width: time that the SET signal remains high/low

tRW

Reset Width: time that the RESET signal remains high/low

0.3 ns

-

0.3 ns

-

SET

D

Q

CLK

RESET

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CLK

SET

RESET

Q

tCWHI (min)

tCWLO (min)

tRESET

tRW

tSET

tSW

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