4/( (FOLSVH( 'DWD 6KHHW 5HY $
&ORFN 6HJPHQW
tPGCKa
tBGCK
7DEOH (FOLSVH( *OREDO &ORFN 'HOD\
3DUDPHWHU
0LQ
Global clock pin delay to quad net
-
Global clock tree delay (quad net to
flip-flop)
-
9DOXH
0D[
1.34 ns
0.56 ns
D :KHQ XVLQJ D 3// W3*&. DQG W%*&. DUH HIIHFWLYHO\ ]HUR GXH WR GHOD\ DGMXVWPHQW E\
3KDVH /RFNHG /RRS
Programmable Clock
External Clock
Global Clock Buffer
Global Clock
tPGCK
Clock
Select
tBGCK
)LJXUH *OREDO &ORFN 6WUXFWXUH 6FKHPDWLF
[9:0]
[17:0]
WA
RE
WD
WE
WCL K
RCLK
[9:0]
RA
[17:0]
RD
ASYNCRD
RAM Module
)LJXUH 5$0 0RGXOH
6\PERO
tSWA
tHWA
tSWD
7DEOH 5$0 &HOO 6\QFKURQRXV :ULWH 7LPLQJ
3DUDPHWHU
9DOXH
0LQ
0D[
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the
active edge of the WRITE CLOCK
0.675 ns
-
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active
edge of the WRITE CLOCK
0 ns
-
WD setup time to WCLK: time the WRITE DATA must be stable before the active
edge of the WRITE CLOCK
0.654 ns
-
Preliminary 4XLFN/RJLF &RUSRUDWLRQ
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