QL6250-E-7PT280M データシートの表示（PDF） - QuickLogic Corporation

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QL6250-E-7PT280M

FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

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tSWE

tHWE

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WD hold time to WCLK: time the WRITE DATA must be stable after the active edge

of the WRITE CLOCK

0 ns

-

WE setup time to WCLK: time the WRITE ENABLE must be stable before the active

edge of the WRITE CLOCK

0.623 ns

-

WE hold time to WCLK: time the WRITE ENABLE must be stable after the active

edge of the WRITE CLOCK

0 ns

-

WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the

time when the data is available at RD

-

4.38 ns

WCLK

WA

tSWA

tHWA

WD

tSWD

tHWD

WE

tSWE

tHWE

RD

old data

new data

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tSRA

RA setup time to RCLK: time the READ ADDRESS must be stable before the active

edge of the READ CLOCK

0.686 ns

-

tHRA

RA hold time to RCLK: time the READ ADDRESS must be stable after the active

edge of the READ CLOCK

0 ns

-

tSRE

RE setup time to WCLK: time the READ ENABLE must be stable before the active

edge of the READ CLOCK

0.243 ns

-

tHRE

RE hold time to WCLK: time the READ ENABLE must be stable after the active

edge of the READ CLOCK

0 ns

-



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