ML145162 データシートの表示（PDF） - LANSDALE Semiconductor Inc.

部品番号

コンポーネント説明

メーカー

ML145162

60 MHz and 85 MHz Universal Programmable Dual PLL Frequency Synthesizers CMOS

LANSDALE Semiconductor Inc. 

ML145162

LANSDALE Semiconductor, Inc.

INPUT PINS

PIN DESCRIPTIONS

register. Details of the counter test mode are in the Tx/Rx

Channel Counter Test section of this data sheet.

OSCin/OSCout

Reference Oscillator Input/Output (Pins 7, 8) These pins

form a reference oscillator when connected to an external par-

allel–resonant crystal. Figure 6 shows the relationship of dif-

ferent crystal frequencies and reference frequencies for cord-

less phone applications in various countries. OSCin may also

serve as input for an externally generated reference signal

which is typically AC coupled.

MCUCLK

System Clock (Pin 5)

This output pin provides a signal of the crystal frequency

(OSCout) divided by 3 or 4 that is controlled by a bit in the

control register.

This signal can be a clock source for the MCU or other sys-

tem clocks.

ADin, Din, CLK, ENB

Auxiliary Data In, Data In, Clock, Enable (Pins 2, 3, 1, 4)

These four pins provide an MCU serial interface for pro-

gramming the reference counter, the transmit–channel count-

er, and the receive–channel counter. They also provide various

controls of the PLL including the power saving mode and the

programming format.

TxPS/fTx, RxPS/fRx

Transmit Power Save, Receive Power Save (Pins 13, 11)

For a normal application, these output pins provide the status

of the internal power saving mode operation. If the

transmit–channels counter circuitry is in power down mode,

TxPS/fTx outputs a high state. If the receive–channels counter

circuitry is in power down mode, RxPS/fRx is set high. These

outputs can be applied for controlling the external power

switch for the transmitter and the receiver to save MCU control

pins.

In the Tx/Rx channel counter test mode, the TxPS/fTx and

RxPS/fRx pins output the divided value of the transmit channel

counter (fTx) and the receive channel counter (fRx), respec-

tively. This test mode operation is controlled by the control

fin–T/fin–R

Transmit/Receive Counter Inputs (Pins 14, 9)

fin–T and fin–R are inputs to the transmit and the receive

counters, respectively. These signals are typically driven from

the loop VCO and AC coupled. The minimum input signal

level is 200 mV p–p @ 60.0 MHz.

OUTPUT PINS

TxPDout/RxPDout

Transmit/Receive Phase Detector Outputs (Pins 15, 10)

These are three–state outputs of the transmit and receive

phase detectors for use as loop error signals (see Figure 7 for

phase detector output wave forms). Phase detector gain

isVDD/4 π volts per radian.

Frequency fV > fR or fV leading: output = negative pulse.

Frequency fV < fR or fV lagging: output = positive pulse.

Frequency fV = fR and phase coincidence: output = high–

impedance state.

NOTE: fR is the divided–down reference frequency at the

phase detector input and fV is the divided–down VCO frequen-

cy at the phase detector input.

LD

Lock Detect (Pin 16)

The lock detect signal is associated with the transmit loop.

The output at a high level indicates an out–of–lock condition

(see Figure 7 for the LD output wave form).

POWER SUPPLY

VDD

Positive Power Supply (Pin 12)

VDD is the most positive power supply potential ranging

from 2.5 to 5.5 V with respect to VSS.

VSS

Negative Power Supply (Pin 6)

VSS is the most negative supply potential and is usually con-

nected to ground.

A

OSCin

N (12 BITS)

fR1

B

4

C

OSCout

M (14 BITS)

25

D

fR2

Page 6 of 24

Crystal

11.150 MHz

11.150 MHz

10.240 MHz

12.000 MHz

N Value

446

223

512

600

fR1→B

6.25 kHz

12.5 kHz

5.0 kHz

5.0 kHz

fR2→C

1.0 kHz

Figure 6. Reference Frequencies for Cordless Phone Applications of Various Countries

www.lansdale.com

Issue 0

Share Link: